ada4830-1 Analog Devices, Inc., ada4830-1 Datasheet - Page 12

• Manufacturer Part Number: ada4830-1
• Description: High Speed Difference Amplifier With Input Short To Battery Protection
• Manufacturer: Analog Devices, Inc.

ADA4830-1
Approximate minimum and maximum CM voltages are shown
in Table 6 for several common supply voltages.
Table 6.
+V
3.0
3.0
3.3
3.3
3.6
3.6
5.0
5.0
1
SHORT TO BATTERY OUTPUT FLAG PIN
The flag output (STB pin) is of an active low, open-drain logic
style. A low level on this output indicates that more than 11 V
has been detected on either the positive or the negative input.
Flags from multiple chips may be wire-or'ed to form a single
fault detection signal. The output is driven by a grounded source
NMOS device, capable of sinking approximately 10 mA while
pulling within 100 mV of ground. The output high level is set
with an external pull-up resistor connected to the supply voltage
of the logic family that is used to monitor the state of the flag.
The speed with which the flag output responds primarily
depends, in the falling direction, on the external capacitance
attached to this node and the sink current that can be provided.
For example, if the load is 10 pF, and the external pull-up voltage is
3.3 V, the fall time is a few nanoseconds. In the rising direction,
Floating (default condition).
S
(V)
–10
–15
15
10
–5
Figure 24. Input Common-Mode Range vs. Supply Voltage
5
0
2.5
VREF PIN FLOATING
V
V
INCM (MAX)
INCM (MIN)
3.0
V
1.5
0.97
1.67
1.15
1.8
1.34
2.5
2.22
REF
1
1
1
1
(V)
3.5
SUPPLY VOLTAGE (V)
4.0
V
–7.0
–4.9
–7.6
–5.6
–8.2
–6.4
–10
–9.9
INCM(MIN)
4.5
5.0
(V)
5.5
V
2.8
4.9
3.6
5.6
4.5
6.4
8.7
9.9
INCM(MAX)
6.0
(V)
Rev. 0 | Page 12 of 16
the speed is determined by external capacitance and the
magnitude of the pull-up resistor. For the case of 10 pF of
external capacitance and a pull-up of 5 kΩ, the time constant
of the rising edge is approximately 50 ns.
Table 7. STB Pin Function
STB Pin Output
High (Logic 1)
Low (Logic 0)
ENABLE/DISABLE MODES (ENA PIN)
The power-down, or enable/disable (ENA) pin, is internally
pulled up to +V
on this pin is high, the amplifier is enabled; pulling ENA low
disables the channel. With no external connection, this pin
floats high, enabling the amplifier channel.
Table 8. ENA Pin Function
ENA Pin Input
High (Logic 1)
Low (Logic 0)
PCB LAYOUT
As with all high speed applications, attention to PCB layout is of
paramount importance. Adhere to standard high speed layout
practices in designs using the ADA4830-1. A solid ground plane
is recommended, and placing a 0.1 µF surface-mount, ceramic
power supply, decoupling capacitor as close as possible to the
supply pin is recommended.
Connect the GND pin(s) to the ground plane with a trace that is
as short as possible. In cases where the
mission lines, series terminate the outputs and use controlled
impedance traces of the shortest length possible to connect to
the signal I/O pins, which should not pass over any voids in the
ground plane.
EXPOSED PADDLE (EPAD) CONNECTION
The
bottom of the package. This pad is not electrically connected
to the die and can be left floating or connected to the ground
plane. Should heat dissipation be a concern, thermal resistance
can be minimized by soldering the EPAD to a metalized pad on
the PCB. Connect this pad to the ground plane with multiple
vias. Note that the thermal resistance (θ
specified with the EPAD soldered to the PCB.
ADA4830-1
S
through a 250 kΩ resistor. When the voltage
has an exposed thermal pad (EPAD) on the
Device State
Normal operation
STB fault condition
Device State
Enabled
Disabled
ADA4830-1
JA
) of the device is
Data Sheet
drives trans-