zxcw8100s28 ETC-unknow, zxcw8100s28 Datasheet - Page 18

• Manufacturer Part Number: zxcw8100s28
• Description: 32 Bit Stereo Direct Drive Digital Audio Amplifier
• Manufacturer: ETC-unknow

DC Dither
A function is provided to help eliminate small signal
digital zero point switching distortion by the addition of
a small DCvoltage. This is intended to move the signal
away from the DACzero to prevent the distortion that is
sometimes discernible when the DAC switches around
zero.
DC dither would be required when using the
recommended HPWM mode. If using RPWM DC dither
would not normally be set, however, the requirement
is application dependant and full details on use are
available in the associated Application document.
Contact your nearest Zetex office for full details.
Bit 36: 0 = DC dither off, 1 = DC dither on
Digital interface select
Bits 44 and 45 select the digital interface standard
required as below:
NOVALOAD™
NOVALOAD™ is selected using bits 34 and 35 as
below:
Bit 34: 0 = NOVALOAD™ off, 1 = NOVALOAD™ on
Bit 35: 0 = remove bass control if bass clips,
NOVALOAD™ limiter attack rate
The limiter attack rate is governed by bits 36 to 39. The
code chosen sets the number of word clock periods to
reduce the gain by 0.5dB. The number of word clock
periods quadruples per digital increment.
Code sequence follow:
The default condition is 0010 which is 4 word clock
periods.
ZXCW8100S28
000
001
010
011
100
101
110
111
S E M I C O N D U C T O R S
1 = adjust volume control if bass clips
=
=
=
=
=
=
=
=
00
01
10
11
1 word clock period per 0.5dB
4 word clock periods per 0.5dB
16 word clock periods per 0.5dB
64 word clock periods per 0.5dB
256 word clock periods per 0.5dB
1024 word clock periods per 0.5dB
4096 word clock periods per 0.5dB
16384 word clock periods per 0.5dB
24 bit I
Left justify 24 or 32 bit
Right justify 16 bit
Right justify 24 bit
2
S
18
NOVALOAD™ limiter release rate
The limiter release rate is governed by bits 40 to 43. The
code chosen sets the number of word clock periods to
reduce the gain by 0.5dB. The number of word clock
periods doubles per digital increment
Code examples in the sequence follow:
The default condition is 1010 which is 16384 word clock
periods.
ATAPI
The ATAPI CD-ROM standard for mixing and muting is
supported by bits 46 to 49. The following logic table
defines how the left and right channels are affected by
the codes set on these bits:
The default setting is 1001 which is left channel = L,
right channel = R
ATI3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0000
0001
0010
1110
1111
1
1
1
1
ATI2
0
0
0
0
0
0
0
0
1
1
1
1
=
=
=
=
=
0
0
1
1
ATI1
0
0
1
1
0
0
1
1
0
0
1
1
16 word clock periods per 0.5dB
32 word clock periods per 0.5dB
64 word clock periods per 0.5dB
262144 word clock periods per 0.5dB
524288 word clock periods per 0.5dB
0
1
0
1
ATI0
0
1
0
1
0
1
0
1
0
1
0
1
ISSUE 3 - NOVEMBER 2003
R
R
R
R
L channel
L
L
L
L
{(L+R)/2}
{(L+R)/2}
{(L+R)/2}
{(L+R)/2}
MUTE
MUTE
MUTE
MUTE
R channel
MUTE
R
L
{(L+R)/2}
MUTE
R
L
{(L+R)/2}
MUTE
R
L
{(L+R)/2}
MUTE
R
L
{(L+R)/2}