lm49350rl National Semiconductor Corporation, lm49350rl Datasheet - Page 32

• Manufacturer Part Number: lm49350rl
• Description: High Performance Audio Codec Sub-system With A Ground-referenced Stereo Headphone Amplifier & An Ultra Low Emi Class D Loudspeaker Amplifier With Dual I2s/pcm Digital Audio Interfaces
• Manufacturer: National Semiconductor Corporation

www.national.com
15.0 Basic PMC Setup Register
This register is used to control the LM49350's Basic Power Management Setup:
1. If the PMC is set to operate from one of the audio ports then it will wait for the port to be enabled or the relevant over ride bit to
be set, forcing the port clock input to enable.
Bits
0
1
2
3
4
5
6
7
PORT1_CLK_OVR
PORT2_CLK_OVR
CHIP_ENABLE
CHIP_ACTIVE
MCLK_OVR
PLL1_ENB
PLL2_ENB
OSC_ENB
Field
When this bit is set the power management will enable the MCLK I/O or internal
oscillator
bias points. When this bit is cleared the PMC will bring the analog down gently and disable
the MCLK or oscillator.
This enables the primary PLL
This enables the secondary PLL
This enables the internal 300kHz Oscillator. For analog only chip modes, the oscillator can
be used instead of an external system clock to drive the chip's power management (PMC).
This forces the MCLK input to enable, regardless of requirement. If set, the audio ports and
digital mixer can be activated even if the chip is in shutdown mode. This assumes that MCLK
is selected as the clock source and that there is an active clock signal driving the MCLK pin.
Setting this bit reduces power consumption, by allowing audio ports and digital mixer to
operate while the analog sections of the chip is powered down.
This forces the clock input of Audio Port 1 input to enable, regardless of other port settings.
This forces the clock input of Audio Port 2 input to enable, regardless of other port settings.
This bit is used to readback the enable status of the chip.
PORT1_CLK_OVR
PORT2_CLK_OVR
TABLE 2. PMC_SETUP (0x00h)
CHIP _ENABLE
PLL1_ENABLE
PLL2_ENABLE
OSC_ENABLE
1
. It will then use this clock to sequence the enabling of the analog references and
MCLK_OVR
0
1
0
1
0
1
0
1
0
1
0
1
0
1
32
Description
PORT_CLK input forced on
PORT_CLK input forced on
I/O control is automatic
I/O control is automatic
I/O control is automatic
MCLK input forced on.
Oscillator Status
Turn Chip Off
Turn Chip On
Oscillator Off
Oscillator On
PLL1 Status
PLL2 Status
Chip Status
Comment
Comment
Comment
PLL1 Off
PLL1 On
PLL2 Off
PLL2 On