isd5216 Winbond Electronics Corp America, isd5216 Datasheet - Page 13

• Manufacturer Part Number: isd5216
• Description: 8 To 16 Minutes Voice Record/playback Device With Integrated Codec
• Manufacturer: Winbond Electronics Corp America

The digital input interface must be selected to either PCM or I
in the configuration register. The compression format must also be selected with bits (LAW1 – LAW0)
in the configuration registers.
The external clock input signal on pin MCLK and the internal clock dividers must be set to values
supporting the selected digital input signal.
The digital smoothing and interpolation filter runs at 3.4 kHz and feeds the 6' D/A converter that can
be switched off to conserve power and reduce noise using the D/A power down bit (DAPD).
The analog output amplifier gain is controlled from configuration registers bits (COG2 – COG0) from -
8 dB to +6 dB.
The ISD5216 has two Master Clock configuration bits that allow four possible Master Clock
frequencies. Bits CKD2 and CKDV set the Master Clock Division ratios. These are bits D12 and D8 of
CFG2, respectively. The combination of these bits, with the sample rate bit HSR0, also set the
CODEC sample frequency as shown in the following table.
7.2.2. Digital Input to Analog Output Path
7.2.3. CODEC External Clock Configuration
*not tested
13.824 MHz
27.648 MHz
13.824 MHz
27.648 MHz
20.48 MHz
40.96 MHz
20.48 MHz
40.96 MHz
F
MCLK
Master Clock Possible Settings
HSR0 (D5)
(CFG2)
0
0
0
0
1
1
1
1
- 13 -
CKD2 (D12)
(CFG2)
0
0
1
1
0
0
1
1
2
S using the interface selector bit (I
Publication Release Date: Jan. 31, 2006
CKDV (D8)
(CFG2)
0
1
0
1
0
1
0
1
44.1 - 48 kHz
11.852 kHz*
11.852 kHz*
44.1-48 kHz
32 kHz*
32 kHz*
F
ISD5216
8 kHz
8 kHz
SCODEC
Revision B.4
2
S0)