pbl386112sht ETC-unknow, pbl386112sht Datasheet - Page 17

• Manufacturer Part Number: pbl386112sht
• Description: Subscriber Line Interface Circuit
• Manufacturer: ETC-unknow

Secondary Protection
The circuit shown in figure 13 utilizes series
resistors together with a programmable
overvoltage protector (e g Power Innova-
tions TISP PBL1 or PBL2), serving as a
secondary protection.
ducting buffered p-gate overvoltage pro-
tector. The protector gate references the
protection (clamping) voltage to negative
supply voltage (i.e. the battery voltage, V
As the protection voltage will track the
negative supply voltage the overvoltage
stress on the SLIC is minimised.
ground by a diode. Negative overvoltages
are initially clamped close to the SLIC neg-
ative supply rail voltage and the protector
will crowbar into a low voltage on-state
condition, by firing an internal thyristor.
ed to carry enough charge to supply a high
enough current to quickly turn on the thyris-
tor in the protector. C
close to the overvoltage protection device.
Without the capacitor even the low induc-
tance in the track to the V
the current and delay the activation of the
thyristor clamp.
be less than 55 mA when using the TISP
PBL1 to ensure that the TISP holding cur-
rent is not exceeded. For higher pro-
grammed line currents, the TISP PBL2 is
recommended.
poses of being non- destructive energy
dissipators, when transients are clamped
and of being fuses, when the line is ex-
posed to a power cross.
The TISP PBLx is a dual forward-con-
Positive overvoltages are clamped to
A gate decoupling capacitor, C
The programmed line current, I
The fuse resistors R
GG
F
serve the dual pur-
should be placed
B
supply will limit
GG
LProg
, is need-
, must
B
).
resistors not sensitive to temperature in
series with PTC´s since the PTC acts as a
capacitance for transients. Otherwise the
SLIC is not protected properly.
Power-up Sequence
No special power-up sequence is neces-
sary except that ground has to be present
before all other power supply voltages.
pull-up terminals.
Printed Circuit Board Layout
Care in Printed Circuit Board (PCB) layout
is essential for proper function;
input should be placed in close proximity to
that pin, such that no interference is inject-
ed into the RSN pin. Ground plane sur-
rounding the RSN pin is advisable.
nected to battery ground (BGND) on the
PCB in one point.
AGND with short leads. Pin LP, pin PSG
and pin AOV are sensitive to leakage cur-
rents. Pin AOV should be surrounded by a
guardring connected to AGND.
be short and very close to each other.
wide leads.
Note that it is always important to use
The digital inputs C1 to C3 are internal
The components connecting to the RSN
Analog ground (AGND) should be con-
R
R
C
LC
SG
B
and C
and C
and R
B2
LP
must be connected with short
REF
connections to VBAT should
should be connected to
Notes
Note 11 .
2.5 V
if AOV-pin is connected to AGND.
Note 12 .
R
and PSRR performance in resistive loop
region (reference D in figure 14). Better
PSRR performance can be achieved by
increasing C
Note 13.
If the momentary value of the current in
TIPX-pin or RINGX-pin exceeds 85mA
harmonic distortion specification can be
derated.
Note 14.
The accurate equation for R
R
Note 15.
5.3V when AOV-pin is not connected, 3.9V
when AOV-pin is connected to AGND.
Note 16.
1.6V
if AOV-pin is connected to AGND.
Note 17.
6.1V when AOV-pin is left open, 4.2V when
AOV-pin is connected to AGND.
Feed
LC
=
RMS
Peak
lower than 2x50
I
500
LProg
if AOV-pin is left open and 0.4V
if AOV-pin is left open and 0.6 V
-
LP
10.4
and C
•
In (I
I
LProg
PBL 386 11/2
HP
.
LProg
will reduce noise
•
LC
32)
is:
Peak
RMS
17