tp11368 National Semiconductor Corporation, tp11368 Datasheet - Page 3

• Manufacturer Part Number: tp11368
• Description: Octal Adaptive Differential Pcm Processor
• Manufacturer: National Semiconductor Corporation

Pin Descriptions
QSEL0, QSEL1
ADPCM bit rate select inputs. The QSEL0 and QSE1 signals
are strobed in with the falling edge of CE. The QSEL0 and
QSEL1 select the conversion bit rate of the PCM data just
clocked in at the TSI input or the bit rate of the ADPCM data
just clocked in at the RSI input. See Table 1 .
RSTB
Chip reset input. A low to high transition at RSTB initiates the
reset sequence which initializes the channel variables for all
16 channels. A logic low applied to this pin sets the
transcoder into a low power dissipation mode. RSTB should
be pulled high for normal operation.
Functional Description
Adaptive Differential Pulse Code Modulation (ADPCM) is a
transcoding algorithm for voice and voice band data trans-
mission. The use of ADPCM reduces the channel bandwidth
requirements from the standard 64 kbps PCM signal by a
factor of two or more. It is used for converting a 64 kbps
A-law or µ-law PCM channel to and from a 40, 32, 24 or
16 kbps channel. The 8-bit PCM signal is reduced to 2–5 bits
ADPCM signal depending on the selected bit rate in the en-
coder.
The TP11368 meets the ITU (CCITT) G.726 recommenda-
tion for 40, 32, 24, and 16 kbps ADPCM, as well as ANSI
T1.301 for 32 kbps. Each channel can be operated with an
independently selectable bit rate determined by QSEL1 and
QSEL0 (see Table 1 ).
The ADPCM encoder converts the 64 kbps A-law or µ-law
PCM input signal to a uniform PCM signal which is sub-
tracted from an estimated signal obtained from an adaptive
predictor. A 31-, 15-, 7-, or 4-level non-uniform quantizer is
used to assign five, four, three or two binary digits, respec-
tively, to the value of the difference signal for transmission.
The ADPCM decoder reconstructs the original PCM signal
by adding the received quantized signal to the signal estima-
tion calculated by the predictor. A synchronous coding ad-
justment unit prevents cumulative distortion occurring on
synchronous tandem codings (ADPCM-PCM-ADPCM) un-
der certain conditions.
The adaptive predictor consists of two independent predictor
structures. One structure uses a second order recursive filter
which models the poles, and the other uses a sixth order
non-recursive filter which models the zeros in the input sig-
nal. This dual structure enables effective handling of both
speech and voice band data signals.
ADPCM PROCESSING
ADPCM to PCM Decoding Operation
When a logic “0” of TRB is latched in with the falling edge of
CE, the ADPCM processor is set to the decoding mode. Data
applied at the RSI input is sampled with the falling edge of
QSEL1
0
0
1
1
TABLE 1. Bit Rate Selection
QSEL0
0
1
0
1
(Continued)
ADPCM Bit Rate
32 kbps
24 kbps
16 kbps
40 kbps
3
TST0, TST1, TST2
Test inputs for factory testing purposes. TST0–2 should be
tied low for normal operation.
V
Positive power supply input pins. V
bypass capacitor should be connected between V
GND1, and V
GND1, GND2
Ground input pins.
NC
Not connected.
ASCK into a 5-bit ADPCM serial register. Within the next
cycle of CE, the decoder converts the ADPCM input data to
an 8-bit companded PCM data after 123 master clocks
(CLK). The 8-bit parallel PCM data is loaded into a
parallel-to-serial shift register and shifted out at the RSO out-
put with the rising edges of PSCK.
PCM to ADPCM Encoding Operation
A logic “1” of TRB at the falling edge of CE sets the ADPCM
processor to the encoding mode. Data applied at the TSI in-
put is sampled in an internal 8-bit PCM register with the fall-
ing edge of PSCK. During the next cycle of CE, the encoder
converts the companded 8-bit PCM data into a 5-, 4-, 3- or
2-bit ADPCM data, which will be shifted out during the third
cycle of CE at the TSO output with the rising edges of ASCK.
The TP11368 requires one master clock signal CLK. The
master clock signal CLK is not required to be synchronous to
the serial I/O clocks ASCK or PSCK. The serial interface
uses the serial clocks ASCK and PSCK and chip enable CE
for receiving and transmitting data. The data is internally
synchronized to the master clock CLK. There is a lower limit
of the clock frequency for CLK resulting from the number of
clock cycles required for processing the data. Table 2 shows
the required clock cycles per channel depending on the se-
lected mode.
The sampling period (usually 125 µs for 8 kHz frame) divided
by the number of CLK cycles gives the required minimum
CLK period. A slightly higher CLK frequency is used in order
to allow for jitter and inaccuracies in the CLK rate. As an ex-
ample, for an eight channel ADPCM codec, CLK frequency
is 16 MHz as shown in the following calculations:
The period of CE must be equal to or greater than the re-
quired number of CLK cycles times the period of CLK. CE
must be low for more than 4 CLK cycles.
Decoder
Encoder
Initialized Channel
Disabled Channel
CC1
t
f
f
, V
Mode of Operation
CLK
CLKmin
CLKnom
CC2
= 125 µs/(16
= 1/t
= 16.0 MHz
CC2
TABLE 2. Processing Cycles
CLK
and GND2.
= 15.75 MHz
*
123) = 63.5 ns
CLK Cycles Needed
CC
= 5V
123
123
45
4
±
5%. A 0.1 µF
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CC1
and