hc55171b Intersil Corporation, hc55171b Datasheet - Page 7

• Manufacturer Part Number: hc55171b
• Description: Low Cost 5 Ren Ringing Slic For Isdn Modem/ta And Wl
• Manufacturer: Intersil Corporation

The voltages listed in the tables are driven from a logic
source that will not drive the ringing input negative. If the
ringing input is driven negative by 200mV, the peak-to-peak
ringing amplitudes can be increased.
Ringing Voltage Limiting Factors
As the load impedance decreases (increasing REN), the
source impedance of the SLIC during ringing slightly
attenuates the ringing signal.
If additional surge protection resistance must be used with
the trapezoidal circuit, the loop length performance of the
circuit will decrease proportionally to the added resistance
in the Tip and Ring leads. For example if 30
resistors is used in each of the Tip and Ring leads, the
ringing loop length will decrease by a total of 60
Low Level Ringing Interface
The trapezoidal application circuit only requires a cadenced
logic signal applied to the wave shaping RC network to
achieve ringing. When not ringing, the logic signal should be
held low. When the logic signal is low, Tip will be near
ground and Ring will be near battery. When the logic signal
is high, Tip will be near battery and Ring will be near ground.
Loop Detector Interface
The RTD output should be monitored for off hook detection
during the ringing period. At all other times, the SHD should
be monitored for off hook detection. The application circuit
can be modified to redirect the ring trip information through
the SHD interface. The change can be made by rewiring the
application circuit, adding a pullup resistor to pin 23 and set-
ting F0 low for the entire duration of the ringing period. The
modifications to the application circuit for the single detector
interface are shown in Figure 1.
SLIC Operating State During Ringing
The SLIC control pin F1 should always be a logic high during
ringing. The control pin F0 will either be a constant logic high
(two detector interface) or a logic low (single detector
TABLE 3. CREST FACTOR PROGRAMMING RESISTOR FOR
TABLE 4. CREST FACTOR PROGRAMMING RESISTOR FOR
R
R
1040
1129
660
740
TRAP
TRAP
0
0
V
V
BAT
BAT
1.10
1.15
1.20
1.10
1.15
1.20
CF
CF
= -65V
= -60V
RMS
RMS
52.5
49.8
47.8
48.2
45.6
43.7
69
R
R
1330
1600
1800
1460
1760
2030
TRAP
TRAP
1.25
1.30
1.35
1.25
1.30
1.35
CF
CF
protection
RMS
RMS
45.9
44.1
42.5
42.0
40.4
38.8
HC55171B
interface). Figure 2 shows the control interface for the dual
detector interface and the single detector interface.
Additional Application Information
Transhybrid Balance
Since the receive signal and its echo are 180 degrees out of
phase, the summing node of an operational amplifier can be
used to cancel the echo. Nearly all CODECs have an inter-
nal amplifier for echo cancellation. The circuit in Figure 3
shows the cancellation amplifier circuit.
VALID DET
VALID DET
FIGURE 1. APPLICATION CIRCUIT WIRING FOR SINGLE
HC55171B
MODE
MODE
V
V
RING
RING
FIGURE 3. TRANSHYBRID AMPLIFIER CIRCUIT
F1
F0
F1
F0
FIGURE 2. DETECTOR LOGIC INTERFACES
V
OUT1
V
LOOP DETECTOR INTERFACE
ACTIVE
ACTIVE
RX
V
(LOGIC HI)
(LOGIC HI)
SHD
(LOGIC HI)
(LOGIC HI)
SHD
RDO 21
RING
RDI 20
NU 23
24
(SINGLE DETECTOR INTERFACE)
(DUAL DETECTOR INTERFACE)
R
R
A
B
D
ADDITIONAL PULL UP RESISTOR
TRAP
RINGING
RTD
RINGING
SHD
R
+
-
F
V
CC
C
R
TRAP
TRAP
VO
V
RING
ACTIVE
ACTIVE
SHD
SHD