pef2045 Infineon Technologies Corporation, pef2045 Datasheet - Page 37

• Manufacturer Part Number: pef2045
• Description: Memory Time Switch Cmos Mtsc
• Manufacturer: Infineon Technologies Corporation

4.2
Access: Read at address 0
B
Z
R
4.3
(Read or Write Operation with Address A0 = 1)
An indirect access is performed by reading/writing three consecutive bytes (first byte = control byte,
second byte = data byte, third byte = address byte) to/from IAR. The structure is shown in table 12.
Table 12
The 3 Bytes of the Indirect Access
Bit 7
0
D7
IA7
The control byte bits K1, K0, C1 and C0 together with the address byte determine the type of access
being performed according to table 13.
Semiconductor Group
Status Register (STA)
Indirect Access Register (IAR)
DB 7
B
0
D6
IA6
Busy: The chip is busy resetting the connection memory (B = 1). B is undefined after
power up and logical 0 after the device initialization.
Note: The maximum time for resetting the connection memory is 250 s.
Incomplete instruction; a three byte indirect instruction is not completed (Z = 1).
Z is 0 after power up.
Note: Z is reset and the indirect access is cancelled by setting MOD:RI or resetting
MOD:RC.
Initialization Request. The connection memory has to be reset due to loss of data
(R = 1). The R bit is set after power failure or inappropriate clocking and reset when the
connection memory reset is finished. R is undefined after power up and logical 0 after
the device initialization.
K1
D5
IA5
K0
D4
IA4
0
D3
IA3
0
D2
IA2
37
C1
D1
IA1
C0
D0
IA0
Bit 0
Control Byte
Data Byte
Address Byte
Z
DB 0
PEB 2045
PEF 2045