adv3002 Analog Devices, Inc., adv3002 Datasheet
adv3002
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adv3002 Summary of contents
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... HPD_D PRODUCT HIGHLIGHTS 1. Input cable equalizer enables use of long cables at the input. For a 24 AWG cable, the ADV3002 compensates for more than data rates up to 2.25 Gbps. 2. Auxiliary multiplexer isolates and buffers the DDC bus and the CEC line, increasing total system capacitance limit. ...
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... CEC Buffer .................................................................................. 15 Hot Plug Detect Control ........................................................... 15 Loss of Signal Detect .................................................................. 16 Serial Control Interface ................................................................. 17 Reset ............................................................................................. 17 Write Procedure .......................................................................... 17 Read Procedure ........................................................................... 18 ADV3002 Register Map ................................................................. 19 Applications Information .............................................................. 21 HDMI Multiplexer for Advanced TV ..................................... 21 Cable Lengths and Equalization ............................................... 24 PCB Layout Guidelines .............................................................. 24 Outline Dimensions ....................................................................... 27 Ordering Guide .......................................................................... 27 Rev Page ...
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... Single-ended high speed channel DR = 2.25 Gbps Single-ended Single-ended LOS_FC (see Figure 27) Clock rate = 225 MHz, LOS_THR = 00 (see Figure 27 pF kΩ LOAD PULL- pF kΩ LOAD PULL-UP Rev Page ADV3002 Min Typ Max 2.25 225 10 − 150 1200 AVCC − 800 AVCC AVCC − ...
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... Output High Voltage Output Low Voltage The total load current includes current drawn by the ADV3002 as well as external devices powered from the AMUXVCC supply. The ADV3002 I C control and logic input pins are listed as control in the Type column in Table 1500 pF kΩ ...
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... JEDEC circuit board for surface-mount packages. θ is specified for the exposed pad soldered to the circuit board < AMUXVCC + 0 with no airflow. < 4 < 4 Table 5. Thermal Resistance Package Type < AMUXVCC + 0.3 V 80-Lead LQFP (ST-80-2) IN ESD CAUTION < AVCC + 0 Rev Page ADV3002 θ θ Unit JA JC 51.3 15.3 °C/W ...
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... IN_A_DATA0+ 17 AVCC 18 IN_A_DATA1– 19 IN_A_DATA1 PIN 1 ADV3002 TOP VIEW (Not to Scale Figure 2. Pin Configuration Rev Page IN_C_DATA2 IN_C_DATA2– ...
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... High Speed TMDS Input C Clock. TMDS High Speed TMDS Input C Data Complement. TMDS High Speed TMDS Input C Data. HPD Hot Plug Detect Output D. TMDS High Speed TMDS Input C Data Complement. TMDS High Speed TMDS Input C Data. HPD Hot Plug Detect Output C. Rev Page ADV3002 ...
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... ADV3002 Pin No. Mnemonic 59 IN_C_DATA2− 60 IN_C_DATA2+ 61 EDID_SCL 62 EDID_SDA 63 EDID_ENABLE 64 AMUXVCC 65 CEC_OUT 66 CEC_IN 67 DDC_SCL_COM 68 DDC_SDA_COM 69 DDC_SCL_D 70 DDC_SDA_D 71 DDC_SCL_C 72 DDC_SDA_C 73 DDC_SCL_B 74 DDC_SDA_B 75 DDC_SCL_A 76 DDC_SDA_A 77 P5V_D 78 P5V_C 79 P5V_B 80 P5V_A Type Description TMDS High Speed TMDS Input C Data Complement. TMDS High Speed TMDS Input C Data. ...
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... Figure 3. Test Circuit for Eye Diagrams Rev Page − 1, ADV3002 SERIAL DATA EVALUATION ANALYZER BOARD SMA COAX CABLE TP2 TP3 0.167UI/DIV AT 2.25Gbps Figure 6. Eye Diagram at TP3 for 2 m Cable 0.167UI/DIV AT 2.25Gbps Figure 7. Eye Diagram at TP3 for AWG Cable ADV3002 ...
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... ADV3002 1.0 ALL CABLES = 24 AWG 0.9 0.8 0.7 1080p, 12-BIT 0.6 1080p, 10-BIT 1080p, 8-BIT 0.5 720p 0.4 0.3 0.2 0 INPUT CABLE LENGTH (m) Figure 8. Deterministic Jitter vs. Input Cable Length 100 DETERMINISTIC JITTER RANDOM JITTER 0 0 0.5 1.0 1.5 2.0 DATA RATE (Gbps) Figure 9. Jitter vs. Data Rate 100 ...
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... Figure 18. DDC, CEC, HPD Output Logic Low Voltage vs. Load Current 70 80 Rev Page DETERMINISTIC JITTER RANDOM JITTER 2.2 2.4 2.6 2.8 3.0 3.2 3.4 INPUT COMMON-MODE VOLTAGE (V) Figure 17. Jitter vs. Input Common-Mode Voltage DDC CEC HPD LOAD CURRENT (mA) ADV3002 3.6 10 ...
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... No specific cable length is suggested for a particular equalization setting because cable performance varies widely between manufacturers; however, in general, the equalization of the ADV3002 can be set without degrading the signal integrity, even for short input cables. TMDS OUTPUT CHANNELS Each high speed output differential pair is terminated to the 3.3 V power supply through a pair of 50 Ω ...
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... The ADV3002 stores the EDID information in an on-chip SRAM. This enables the EDID information to be simultaneously accessible to all four HDMI ports. The ADV3002 combines the 5 V power from the four HDMI sources such that the EDID information can be available even when the system power is off. A block diagram of the ADV3002 DDC buffering and EDID replication scheme is shown in Figure 23 ...
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... In HDTV applications where the CEC function is available, the EDID contains the source physical address (SPA); a unique value for each HDMI port. Because the memory in the ADV3002 is volatile, the SPA must be stored in the external EDID EEPROM. Rather than require a larger external EEPROM to store the SPA, ...
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... ADV3002 copies the contents of the external EDID EEPROM into the on-chip SRAM. While the EDID is being copied, the HPD signals for all four ports are held low by the ADV3002. A flowchart of the start-up procedure is shown in Figure 25. The entire start-up procedure takes less than 10 ms. The EDID replication feature can be disabled using the EDID_ENABLE pin ...
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... LOS_STATUS bit indicates an active input. Three conditions need to be fulfilled for an HDMI input to be considered active: • The TMDS input termination resistors must be enabled. By default, the ADV3002 TMDS input termination resistors are enabled only on the selected input. • The TMDS clock frequency exceeds the frequency cutoff (LOS_FC) ...
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... SERIAL CONTROL INTERFACE RESET On initial power-up any point in operation, the ADV3002 register set can be restored to the default values by pulling the RESETB pin low according to the specification in Table 3. During normal operation, however, the RESETB pin must be pulled up to 3.3 V. WRITE PROCEDURE To write data to the ADV3002 register set microcontroller) needs to send the appropriate control signals to the ADV3002 slave device ...
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... To read data from the ADV3002 register set microcontroller) needs to send the appropriate control signals to the ADV3002 slave device. The signals are controlled by the I master unless otherwise specified. For a diagram of the procedure, see Figure 29. The steps for a read procedure are as follows: 1 ...
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... HPD_CTL[3:0] 3:0 HPD_CTL[3:0] 0000: HPD outputs are high impedance (pulled via external resistor) 0001: HPD_A = low if HPD_SRC = 1 0010: HPD_B = low if HPD_SRC = 1 0100: HPD_C = low if HPD_SRC = 1 1000: HPD_D = low if HPD_SRC = 1 1111: all HPD outputs = low if HPD_SRC = 1 Rev Page ADV3002 ...
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... ADV3002 Register Address Default Name 0x07 0x00 Loss of signal detect control 0x0E 0x00 EDID replication mode (write only) 0x0F 0x00 EDID EEPROM write protect password (write only) 0x10 0x00 Loss of signal detect status 0xFE 0x03 Revision 0xFF 0xC2 Device ID Bit Bit Name ...
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... Additionally, the ADV3002 includes an EDID replication function that enables one EDID EEPROM to be shared for all four HDMI ports. Alternatively, a system standby microcontroller can be used instead of a dedicated EDID EEPROM to load the ADV3002 SRAM. Simplified application schematics are shown in Figure 33 and Figure 34 illustrating these two options. ...
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... OUT_DATA0+ OUT_DATA0– OUT_CLK+ IN_B_DATA2+ OUT_CLK– IN_B_DATA2– IN_B_DATA1+ IN_B_DATA1– IN_B_DATA0+ IN_B_DATA0– DDC_SCL_COM IN_B_CLK+ DDC_SDA_COM IN_B_CLK– P5V_B ADV3002 47kΩ HPD_B DDC_SCL_B DDC_SDA_B CEC_IN I2C_SCL I2C_SDA IN_C_DATA2+ I2C_ADDR[1:0] IN_C_DATA2– CEC_OUT IN_C_DATA1+ 10kΩ IN_C_DATA1– IN_C_DATA0+ IN_C_DATA0– ...
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... CEC_OUT 10kΩ OPTIONAL AMUXVCC 10kΩ 3.3V STANDBY EDID_ENABLE 2kΩ 2kΩ EDID_SCL EDID_SDA AMUXVCC 10kΩ RESETB TX_EN SEL[1:0] 1µF AVEE Rev Page ADV3002 D2+ D2– D1+ D1– D0+ HDMI D0– Rx CLK+ CLK– DDC_SCL DDC_SDA 2kΩ MCU 3.3V STANDBY EDID EEPROM ...
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... Receiver sensitivity: the sensitivity of the terminating receiver. As such, no particular equalizer setting is recommended for specific cable types or lengths. In nearly all applications, the ADV3002 equalization level can be set to high dB, for all input cable configurations at all data rates, without degrading the signal integrity. PCB LAYOUT GUIDELINES The ADV3002 switches two distinctly different types of signals, both of which are required for HDMI and DVI video ...
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... SDA and SCL (serial data and serial clock, respectively). The DDC and CEC signals are buffered and switched through the ADV3002, and the HPD signal is pulsed low by the ADV3002. These signals do not need to be routed with the same strict considerations as the high speed TMDS signals ...
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... When the ADV3002 is powered off, all DDC/CEC inputs are placed in a high impedance state. This prevents contention on the DDC bus, enabling a design to include an EDID in front of the ADV3002. Power Supplies The ADV3002 has two separate power supplies. The supply/ ground pairs are • ...
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... Figure 37. 80-Lead Low Profile Quad Flat Package [LQFP] (ST-80-2) Dimensions shown in millimeters Package Description 80-Lead Low Profile Quad Flat Package [LQFP] 80-Lead Low Profile Quad Flat Package [LQFP], Reel Evaluation Board Rev Page 16.20 16.00 SQ 15. 14.20 TOP VIEW 14.00 SQ 13. 0.38 0.32 0.22 Package Option Ordering Quantity ST-80-2 ST-80-2 1,000 ADV3002 ...
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... ADV3002 NOTES Purchase of licensed I C components of Analog Devices Inc. or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I 2 Patent Rights to use these components system, provided that the system conforms to the I ©2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners ...