ssm2602 Analog Devices, Inc., ssm2602 Datasheet - Page 23

• Manufacturer Part Number: ssm2602
• Description: Low Power Audio Codec
• Manufacturer: Analog Devices, Inc.

Preliminary Technical Data
DIGITAL AUDIO I/F, ADDRESS 0x07
Table 26. Digital Audio I/F Register Bit Map
D8
0
Table 27. Descriptions of Digital Audio I/F Register Bits
Bit Name
BCLKINV
MS
LRSWAP
LRP
WL [1:0]
FORMAT [1:0]
SAMPLING RATE, ADDRESS 0x08
Table 28. Sampling Rate Register Bit Map
D8
0
Table 29. Descriptions of Sampling Rate Register Bits
Bit Name
CLKODIV2
CLKDIV2
SR [3:0]
BOSR
USB
D7
CLKODIV2
D7
BCLKINV
Description
BCLK inversion control
Master mode enable
Swap DAC data control
Polarity control for clocks in right justified, left justified, and
I
Data-word length control
Digital audio input format control
2
S modes
Description
CLKOUT divider select
Core clock divide select
Clock setting condition
Base oversampling rate
USB mode select
D6
MS
D6
CLKDIV2
D5
LRSWAP
Rev. PrB | Page 23 of 28
D5
D4
LRP
Settings
0 = CLKOUT is core clock (default)
1 = CLKOUT is core clock divided by 2
0 = core clock is MCLK (default)
1= core clock is MCLK divided by 2
See Table 30 and Table 31.
USB mode:
0 = 250 f
1 = 272 f
Normal mode:
0 = 256 f
1 = 384 f
0 = USB mode disable (default)
1 = USB mode enable
D4
D3
S
S
S
S
(default)
(default)
SR [3:0]
Settings
0 = BCLK not inverted (default)
1 = BCLK inverted
0 = enable slave mode (default)
1 = enable master mode
0 = output left- and right-channel data as normal
(default)
1 = swap left- and right-channel DAC data in audio
interface
0 = normal DACLRC and ADCLRC (default), or DSP
Submode 1
1 = invert DACLRC and ADCLRC polarity, or DSP
Submode 2
00 = 16 bits
01 = 20 bits
10 = 24 bits (default)
11 = 32 bits
00 = right justified
01 = left justified
10 = I
11 = DSP mode
D3
WL [1:0]
2
S format (default)
D2
D2
D1
D1
BOSR
FORMAT [1:0]
SSM2602
D0
D0
USB