74ahct164bq NXP Semiconductors, 74ahct164bq Datasheet
74ahct164bq
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74ahct164bq Summary of contents
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Rev. 02 — 29 November 2006 1. General description The 74AHC164; 74AHCT164 shift register is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL specified in compliance ...
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... C to +125 C 74AHC164PW +125 C 74AHC164BQ +125 C 74AHCT164 74AHCT164D +125 C 74AHCT164PW +125 C 74AHCT164BQ +125 C 4. Functional diagram Fig 1. Functional diagram 74AHC_AHCT164_2 Product data sheet 74AHC164; 74AHCT164 Description SO14 plastic small outline package; 14 leads; body width 3.9 mm TSSOP14 plastic thin shrink small outline package ...
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... NXP Semiconductors DSA 1 2 DSB 001aac423 Fig 2. Logic symbol DSA DSB FF1 Fig 4. Logic diagram 74AHC_AHCT164_2 Product data sheet 74AHC164; 74AHCT164 Fig 3. IEC logic symbol ...
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... NXP Semiconductors 5. Pinning information 5.1 Pinning Fig 5. Pin configuration SO14 and 5.2 Pin description Table 2. Pin description Symbol Pin DSA 1 DSB GND 74AHC_AHCT164_2 Product data sheet DSA ...
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... NXP Semiconductors 6. Functional description [1] Table 3. Function table Operating mode Reset (clear) Shift [ HIGH voltage level HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition LOW voltage level LOW voltage level one set-up time prior to the LOW-to-HIGH clock transition; ...
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... NXP Semiconductors 8. Recommended operating conditions Table 5. Recommended operating conditions Symbol Parameter 74AHC164 V supply voltage CC V input voltage I V output voltage O T ambient temperature amb t/ V input transition rise and fall rate 74AHCT164 V supply voltage CC V input voltage I V output voltage O T ambient temperature ...
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... NXP Semiconductors Table 6. Static characteristics 74AHC164 At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter I supply current CC C input capacitance +85 C amb V HIGH-level input voltage IH V LOW-level input voltage IL V HIGH-level output voltage OH V LOW-level output voltage ...
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... NXP Semiconductors Table 6. Static characteristics 74AHC164 At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter V LOW-level output voltage OL I input leakage current I I supply current CC Table 7. Static characteristics 74AHCT164 At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol ...
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... NXP Semiconductors Table 7. Static characteristics 74AHCT164 At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter I additional supply current +125 C amb V HIGH-level input voltage IH V LOW-level input voltage IL V HIGH-level output voltage OH V LOW-level output voltage OL I input leakage current ...
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... NXP Semiconductors 10. Dynamic characteristics Table 8. Dynamic characteristics 74AHC164 Voltages are referenced to GND (ground = 0 V); for the test circuit see Symbol Parameter Conditions HIGH-to-LOW CP to Qn; see PHL propagation V CC delay Qn; see LOW-to-HIGH CP to Qn; see ...
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... NXP Semiconductors Table 8. Dynamic characteristics 74AHC164 Voltages are referenced to GND (ground = 0 V); for the test circuit see Symbol Parameter Conditions t hold time DSA, DSB to CP; h see Figure recovery time MR to CP; see rec maximum see Figure 7 max ...
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... NXP Semiconductors Table 9. Dynamic characteristics 74AHCT164 Voltages are referenced to GND (ground = 0 V); for the test circuit see Symbol Parameter Conditions t LOW-to-HIGH CP to Qn; see PLH propagation delay t pulse width CP HIGH or LOW; W see Figure 7 t pulse width MR; see WL LOW t set-up time DSA, DSB to CP; ...
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... NXP Semiconductors 11. Waveforms CP input Qn output Measurement points are given in V and V are typical voltage output drop that occur with the output load Fig 7. The clock (CP) to output (Qn) propagation delays, the clock (CP) pulse width and the maximum clock (CP) frequency MR input CP input ...
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... NXP Semiconductors CP input DSA, DSB input Qn output Measurement points are given in The shaded areas indicate when the input is permitted to change for predictable output performance. V and V are typical voltage output drop that occur with the output load Fig 9. The data set-up and hold times for the (DSA and DSB) inputs Table 10 ...
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... NXP Semiconductors 12. Package outline SO14: plastic small outline package; 14 leads; body width 3 pin 1 index 1 e DIMENSIONS (inch dimensions are derived from the original mm dimensions) A UNIT max. 0.25 1.45 mm 1.75 0.25 0.10 1.25 0.010 0.057 inches 0.01 0.069 0.004 0.049 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. ...
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... NXP Semiconductors TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4 pin 1 index 1 e DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 0.95 mm 1.1 0.25 0.05 0.80 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. ...
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... NXP Semiconductors DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 14 terminals; body 2 0.85 mm terminal 1 index area terminal 1 index area DIMENSIONS (mm are the original dimensions) (1) A UNIT max. 0.05 0. 0.2 0.00 0.18 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. ...
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... NXP Semiconductors. • Legal texts have been adapted to the new company name where appropriate. • The dynamic characteristics table has been reformatted. • Type numbers 74AHC164BQ and 74AHCT164BQ (package DHVQFN14) have been added. 74AHC_AHCT164_1 20000815 (9397 750 07332) 74AHC_AHCT164_2 Product data sheet 74AHC164 ...
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... For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail ...
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... NXP Semiconductors 16. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 6 Functional description . . . . . . . . . . . . . . . . . . . 5 7 Limiting values Recommended operating conditions Static characteristics Dynamic characteristics . . . . . . . . . . . . . . . . . 10 11 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 15 13 Revision history ...