adg3304 Analog Devices, Inc., adg3304 Datasheet - Page 18

• Manufacturer Part Number: adg3304
• Description: Low Voltage, 1.15 V To 5.5 V, 4-channel, Bidirectional Logic Level Translator
• Manufacturer: Analog Devices, Inc.

ADG3304
APPLICATIONS
The ADG3304 is designed for digital circuits that operate at
different supply voltages; therefore, logic level translation is
required. The lower voltage logic signals are connected to the
A pins, and the higher voltage logic signals are connected to the
Y pins. The ADG3304 can provide level translation in both
directions from A→Y or Y→A on all four channels, eliminating
the need for a level translator IC for each direction. The internal
architecture allows the ADG3304 to perform bidirectional level
translation without an additional signal to set the direction in
which the translation is made. It also allows simultaneous data
flow in both directions on the same part, for example, when two
channels translate in A→Y direction while the other two translate
in Y→A direction. This simplifies the design by eliminating the
timing requirements for the direction signal and reducing the
number of ICs used for level translation.
Figure 40 shows an application where two microprocessors
operating at 1.8 V and 3.3 V, respectively, can transfer data
simultaneously using two full-duplex serial links, TX1/RX1
and TX2/RX2.
When the application requires level translation between a micro-
processor and multiple peripheral devices, the ADG3304 I/O
pins can be three-stated by setting EN = 0. This feature allows
the ADG3304 to share the data buses with other devices without
causing contention issues. Figure 41 shows an application where
a 1.8 V microprocessor is connected to a 3.3 V peripheral
device using the three-state feature.
MICROCONTROLLER/
MICROPROCESSOR/
DSP
1.8V
GND
Figure 40. 1.8 V to 3.3 V Level Translation Circuit on
TX1
RX1
TX2
RX2
Two Full-Duplex Serial Links
100nF
V
A1
A2
A3
A4
EN
CCA
ADG3304
V
GND
CCY
Y1
Y2
Y3
Y4
100nF
GND
RX1
RX2
TX1
TX2
MICROCONTROLLER/
MICROPROCESSOR/
3.3V
DSP
Rev. B | Page 18 of 20
LAYOUT GUIDELINES
As with any high speed digital IC, the printed circuit board
layout is important for the overall performance of the circuit.
Care should be taken to ensure proper power supply bypass and
return paths for the high speed signals. Each V
V
(ESR) and effective series inductance (ESI) capacitors placed as
close as possible to the V
inductance of the high speed signal track may cause significant
overshoot. This effect can be reduced by keeping the length of
the tracks as short as possible. A solid copper plane for the
return path (GND) is also recommended.
CCY
MICROCONTROLLER/
) should be bypassed using low effective series resistance
MICROPROCESSOR/
GND
DSP
1.8V
Figure 41. 1.8 V to 3.3 V Level Translation Circuit
CS
I/O
I/O
I/O
I/O
L1
L2
L3
L4
Using the Three-State Feature
CCA
100nF
100nF
pin and the V
V
A1
A2
A3
A4
EN
V
A1
A2
A3
A4
EN
CCA
CCA
ADG3304
ADG3304
V
V
GND
GND
CCY
CCY
Y1
Y2
Y3
Y4
Y1
Y2
Y3
Y4
100nF
100nF
CCY
pin. The parasitic
CC
GND
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
pin (V
H1
H2
H3
H4
H1
H2
H3
H4
PERIPHERAL
PERIPHERAL
3.3V
3.3V
DEVICE 1
DEVICE 2
CCA
and