adg3247bru-u1 Analog Devices, Inc., adg3247bru-u1 Datasheet
adg3247bru-u1
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adg3247bru-u1 Summary of contents
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... Extremely low propagation delay through switch 3. 4.5 W switches connect inputs to outputs 4. Level/voltage translation 5. 40-lead LFCSP and 38-lead TSSOP packages is CC One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 Fax: 781/326-8703 © 2003 Analog Devices, Inc. All rights reserved. ADG3247 B15 www.analog.com ...
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ADG3247–SPECIFICATIONS Parameter DC ELECTRICAL CHARACTERISTICS Input High Voltage Input Low Voltage Input Leakage Current OFF State Leakage Current ON State Leakage Current Maximum Pass Voltage 3 CAPACITANCE A Port Off Capacitance B Port Off Capacitance A, B Port On Capacitance ...
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... Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C Model Temperature Range ADG3247BCP –40°C to +85°C ADG3247BCP-REEL7 –40°C to +85°C ADG3247BRU –40°C to +85°C ADG3247BRU-REEL7 –40°C to +85°C Table I. Pin Description Mnemonic Description BEx Bus Enable (Active Low) SEL Level Translation Select Ax ...
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ADG3247 V Positive Power Supply Voltage. CC GND Ground (0 V) Reference. V Minimum Input Voltage for Logic 1. INH V Maximum Input Voltage for Logic 0. INL I Input Leakage Current at the Control Inputs OFF State ...
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SEL = 3. 3. 0.5 1.0 1.5 2.0 2.5 3.0 3 ...
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ADG3247 3 2 2.0 = 3.3V; SEL = 1.5 = SEL = 3. 1.0 0.5 = SEL = 2. ...
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SEL = 3. p 20dB ATTENUATION EYE WIDTH = ((CLOCK PERIOD – 55 JITTER p-p)/CLOCK PERIOD) 100% 50 0.5 0.6 0.7 0.8 0.9 ...
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ADG3247 For the following load circuit and waveforms, the notation that is used OUT PULSE D.U.T. GENERATOR R T NOTES t PULSE GENERATOR FOR ALL PULSES: 2.5ns, R FREQUENCY 10MHz. C INCLUDES BOARD, ...
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BUS SWITCH APPLICATIONS Mixed Voltage Operation, Level Translation Bus switches can be used to provide an ideal solution for inter- facing between mixed voltage systems. The ADG3247 is suitable for applications where voltage translation from 3.3 V technology to a ...
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ADG3247 V OUT 3.3V SUPPLY SEL = 0V 1.8V SWITCH 0V 3.3V INPUT Figure 10. 3 1.8 V Voltage Translation, SEL = 0 V Bus Isolation A common requirement of bus architectures is low capacitance loading of the ...
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PIN 1 INDICATOR 12 MAX 1.00 0.90 0.80 SEATING PLANE 38-Lead Thin Shrink Small Outline Package [TSSOP] PIN 1 0.15 0.05 COPLANARITY REV. 0 OUTLINE DIMENSIONS 40-Lead Lead Frame Chip Scale Package [LFCSP] (CP-40) Dimensions shown in millimeters 6.00 BSC ...
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