adg1414 Analog Devices, Inc., adg1414 Datasheet - Page 19

• Manufacturer Part Number: adg1414
• Description: 9.5 ? Ron ?15 V/+12 V/?5 V Icmos Serially-controlled Octal Spst Switches
• Manufacturer: Analog Devices, Inc.

THEORY OF OPERATION
The ADG1414 is a set of serially controlled, octal SPST switches.
Each of the eight bits of the 8-bit write corresponds to one
switch of the device. A Logic 1 in the particular bit position
turns the switch on, whereas a Logic 0 turns the switch off.
Because each switch is independently controlled by an individual
bit, this provides the option of having any, all, or none of the
switches turned on.
SERIAL INTERFACE
The ADG1414 has a 3-wire serial interface (SYNC, SCLK, and
DIN pins) that is compatible with SPI, QSPI, and MICROWIRE
interface standards, as well as most DSPs. See
timing diagram of a typical write sequence.
The write sequence begins by bringing the SYNC line low. This
enables the input shift register. Data from the DIN line is
clocked into the 8-bit input shift register on the falling edge of
SCLK. The serial clock frequency can be as high as 50 MHz,
making the ADG1414 compatible with high speed DSPs.
Data can be written to the shift register in more or less than
eight bits. In each case, the shift register retains the last eight
bits that were written. When all eight bits have been written
into the shift register, the SYNC line is brought high again. The
switches are updated with the new configuration, and the input
shift register is disabled. With SYNC held high, the input shift
register is disabled; therefore, further data or noise on the DIN
line has no effect on the shift register.
Data appears on the SDO pin on the rising edge of SCLK
suitable for daisy chaining or readback, delayed by eight bits.
INPUT SHIFT REGISTER
The input shift register is eight bits wide (see Table 10). Each bit
controls one switch. These data bits are transferred to the switch
register on the rising edge of SYNC.
Table 10. ADG1414 Input Shift Register Bit Map
MSB
DB7
S8
1
Logic 0 = switch off and Logic 1 = switch on.
DB6
S7
DB5
S6
DB4
S5
DB3
S4
DB2
S3
DB1
S2
Figure 2
1
LSB
DB0
S1
for a
Rev. 0 | Page 19 of 20
POWER-ON RESET
The ADG1414 contains a power-on reset circuit. On power-up
of the device, all switches are in the off condition and the
internal shift register is filled with zeros and remains so until a
valid write takes place.
The part also has a RESET/V
all switches are off and the appropriate registers are cleared to 0.
DAISY CHAINING
For systems that contain several switches, the SDO pin can be
used to daisy-chain several devices together. The SDO pin can
also be used for diagnostic purposes and provide serial readback,
wherein the user can read back the switch contents.
SDO is an open-drain output that should be pulled to the V
supply with an external resistor.
The SCLK is continuously applied to the input shift register
when SYNC is low. If more than eight clock pulses are applied,
the data ripples out of the shift register and appears on the SDO
line. This data is clocked out on the rising edge of SCLK and is
valid on the falling edge. By connecting this line to the DIN
input on the next device in the chain, a multiswitch interface is
constructed. Each device in the system requires eight clock
pulses; therefore, the total number of clock cycles must equal
8N, where N is the total number of devices in the chain.
When the serial transfer to all devices is complete, SYNC is
taken high. This prevents any further data from being clocked
into the input shift register.
The serial clock can be a continuous or a gated clock. A conti-
nuous SCLK source can be used only if SYNC can be held low
for the correct number of clock cycles. In gated clock mode, a
burst clock containing the exact number of clock cycles must be
used, and SYNC must be taken high after the final clock to latch
the data. Gated clock mode reduces power consumption by
reducing the active clock time.
L
pin. When the RESET/V
ADG1414
L
pin is low,
L