adg661 Analog Devices, Inc., adg661 Datasheet - Page 8

• Manufacturer Part Number: adg661
• Description: Lc2mos Precision 5 V Quad Spst Switches
• Manufacturer: Analog Devices, Inc.

ADG661/ADG662/ADG663
Test Circuits (Continued)
V
OUT
V
S
V
S
R
50
L
8. Channel-to-Channel Crosstalk
V
V
IN1
IN
IN
0.1 F
GND
0.1 F
7. Off Isolation
S
GND
D
S
0.1 F
V
V
DD
DD
0.1 F
V
V
DD
DD
V
V
S
D
SS
SS
V
V
D
SS
SS
CHANNEL TO CHANNEL
CROSSTALK = 20
V
IN2
0.006 (0.15)
0.002 (0.05)
SEATING
PLANE
50
NC
0.0256
(0.65)
R
50
BSC
16
1
L
PIN 1
Dimensions shown in inches and (mm).
LOG V
0.201 (5.10)
0.193 (4.90)
OUTLINE DIMENSIONS
V
OUT
0.0118 (0.30)
0.0075 (0.19)
S
/V
16-Lead TSSOP
OUT
(RU-16)
8
9
–8–
0.0433
(1.10)
MAX
0.0035 (0.090)
0.0079 (0.20)
APPLICATION
Figure 9 illustrates a precise, sample-and-hold circuit. An
AD845 is used as the input buffer while the output operational
amplifier is an OP07. During the track mode, SW1 is closed and
the output V
SW1 is opened and the signal is held by the hold capacitor C
Due to switch and capacitor leakage, the voltage on the hold
capacitor will decrease with time. The ADG661/ADG662/
ADG663 minimizes this droop due to its low leakage specifica-
tions. The droop rate is further minimized by the use of a poly-
styrene hold capacitor. The droop rate for the circuit shown is
typically 15 V/ s.
A second switch SW2, which operates in parallel with SW1, is
included in this circuit to reduce pedestal error. Since both
switches will be at the same potential, they will have a differen-
tial effect on the op amp OP07 which will minimize charge
injection effects. Pedestal error is also reduced by the compensa-
tion network R
duces the hold time glitch while optimizing the acquisition time.
Using the illustrated op amps and component values, the pedes-
tal error has a maximum value of 5 mV over the 3 V input
range. The acquisition time is 2.5 ms while the settling time is
1.85 s.
V
IN
AD845
+5V
–5V
8°
0°
Figure 9. Accurate Sample-and-Hold
OUT
0.028 (0.70)
0.020 (0.50)
C
and C
follows the input signal V
S
S
SW1
SW2
C
. This compensation network also re-
+5V
ADG661
ADG662
ADG663
–5V
D
D
75
R
C
2200pF
2200pF
C
1000pF
IN
C
C
H
. In the hold mode,
OP07
+5V
–5V
REV. 0
V
OUT
H
.