adg795gccpz-reel Analog Devices, Inc., adg795gccpz-reel Datasheet - Page 17

• Manufacturer Part Number: adg795gccpz-reel
• Description: I2c-compatible, Wide Bandwidth, Five 2 1 Multiplexer
• Manufacturer: Analog Devices, Inc.

THEORY OF OPERATION
The ADG795A/ADG795G are monolithic CMOS devices
comprising five 2:1 multiplexers controllable via a standard I
serial interface. The CMOS process provides ultralow power
dissipation, yet offers high switching speed and low on resistance.
The on resistance profile is very flat over the full analog input
range, and wide bandwidth ensures excellent linearity and low
distortion. These features, combined with a wide input signal
range, make the ADG795A/ADG795G an ideal switching
solution for a wide range of TV applications.
The switches conduct equally well in both directions when on.
In the off condition, signal levels up to the supplies are blocked.
The integrated serial I
switches (ADG795A/ADG795G) and general-purpose logic
pins (ADG795G only).
The ADG795A/ADG795G have many attractive features, such as
the ability to individually control each multiplexer, the option of
reading back the status of any switch. The ADG795G has one
general-purpose logic output pin controllable through the I
interface. The following sections describe these features in detail.
I
The ADG795A/ADG795G are controlled via an I
serial bus interface (refer to the I
from Philips Semiconductor) that allows the part to operate as a
slave device (no clock is generated by the ADG795A/ADG795G).
The communication protocol between the I
device operates as follows:
1.
2.
2
C SERIAL INTERFACE
The master initiates data transfer by establishing a start
condition (defined as a high-to-low transition on the SDA
line while SCL is high). This indicates that an address/data
stream follows. All slave devices connected to the bus
respond to the start condition and shift in the next eight
bits, consisting of a seven bit address (MSB first) plus an
R/ W bit. This bit determines the direction of the data flow
during the communication between the master and the
addressed slave device.
The slave device whose address corresponds to the trans-
mitted address responds by pulling the SDA line low during
the ninth clock pulse (this is called the acknowledge bit).
At this stage, all other devices on the bus remain idle while
the selected device waits for data to be written to, or read
from, its serial register. If the R/ W bit is set high, the
master reads from the slave device. However, if the R/ W bit
is set low, the master writes to the slave device.
2
C interface controls the operation of the
2
C-Bus Specification available
2
C master and the
2
C-compatible
2
C
Rev. 0 | Page 17 of 24
2
C
3.
4.
I
The ADG795A/ADG795G have a 7-bit I
most significant bits are internally hardwired and last three bits
(A0, A1, and A2) are user-adjustable. This allows the user to
connect up to eight ADG795As/ADG795Gs to the same bus. The
I
7-Bit I
MSB
1
WRITE OPERATION
When writing to the ADG795A/ADG795G, the user must
begin with an address byte and R/ W bit, after which time the
switch acknowledges that it is prepared to receive data by
pulling SDA low. Data is loaded into the device as a 16-bit word
under the control of a serial clock input, SCL. Figure 31
illustrates the entire write sequence for the ADG795A/
ADG795G. The first data byte (AX7 to AX0) controls the status
of the switches while the LDSW and RESETB bits from the
second byte control the operation mode of the device. Table 6
shows a list of all commands supported by the ADG795A/
ADG795G with the corresponding byte that needs to be loaded
during a write operation.
To achieve the desired configuration, one or more commands
can be loaded into the device. Any combination of the
commands in Table 6 can be used with these restrictions:
N
N
2
2
C bit map shows the configuration of the 7-bit address.
C ADDRESS
Data transmits over the serial bus in sequences of nine
clock pulses (eight data bits followed by an acknowledge
bit). The transitions on the SDA line must occur during the
low period of the clock signal, SCL, and remain stable
during the high period of SCL. Otherwise, a low-to-high
transition when the clock signal is high can be interpreted
as a stop event that ends the communication between the
master and the addressed slave device.
After transferring all data bytes, the master establishes a
stop condition, defined as a low-to-high transition on the
SDA line while SCL is high. In write mode, the master pulls
the SDA line high during the 10
stop condition. In read mode, the master issues a no
acknowledge for the ninth clock pulse (the SDA line
remains high). The master then brings the SDA line low
before the 10
clock pulse to establish a stop condition.
Only one switch from a given multiplexer can be on at any
given time.
When a sequence of successive commands affect the same
element (that is, the switch or GPO pin), only the last
command is executed.
2
C Address Configuration
0
th
1
clock pulse, and then high during the 10
0
ADG795A/ADG795G
th
A2
clock pulse to establish a
2
C address. The four
A1
LSB
A0
th