sak-c164ci-l16m3v Infineon Technologies Corporation, sak-c164ci-l16m3v Datasheet - Page 61
![no-image](/images/no-image-200.jpg)
sak-c164ci-l16m3v
Manufacturer Part Number
sak-c164ci-l16m3v
Description
16-bit Single-chip Microcontroller
Manufacturer
Infineon Technologies Corporation
Datasheet
1.SAK-C164CI-L16M3V.pdf
(75 pages)
- Current page: 61 of 75
- Download datasheet (2Mb)
Preliminary
Multiplexed Bus (cont’d)
(Operating Conditions apply)
ALE cycle time = 6 TCL + 2
Parameter
ALE fall. edge to RdCS,
WrCS (no RW delay)
Address float after RdCS,
WrCS (with RW delay)
Address float after RdCS,
WrCS (no RW delay)
RdCS to Valid Data In
(with RW delay)
RdCS to Valid Data In
(no RW delay)
RdCS, WrCS Low Time
(with RW delay)
RdCS, WrCS Low Time
(no RW delay)
Data valid to WrCS
Data hold after RdCS
Data float after RdCS
Address hold after
RdCS, WrCS
Data hold after WrCS
1)
Data Sheet
These parameters refer to the latched chip select signals (CSxL). The early chip select signals (CSxE) are
specified together with the address and signal BHE (see figures below).
t
A
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
43
44
45
46
47
48
49
50
51
52
54
56
+
t
C
CC -6 +
CC –
CC –
CC 51 +
CC 82 +
CC 41 +
CC 43 +
CC 43 +
SR –
SR –
SR 0
SR –
+
t
F
(187.5 ns at 16 MHz CPU clock without waitstates)
min.
Max. CPU Clock
= 16 MHz
t
t
t
t
t
t
57
A
C
C
C
F
F
max.
–
0
31
33 +
64 +
–
–
–
–
43 +
–
–
t
t
t
C
C
F
1 / 2TCL = 1 to 16 MHz
min.
-6
+
–
–
–
–
2TCL - 12
+
3TCL - 12
+
2TCL - 22
+
0
–
2TCL - 20
+
2TCL - 20
+
Variable CPU Clock
t
t
t
t
t
t
A
C
C
C
F
F
C164CI-L16M3V
max.
–
0
TCL
2TCL - 30
+
3TCL - 30
+
–
–
–
–
2TCL - 20
+
–
–
t
t
t
C
C
F
Low Power
V1.0, 2003-01
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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