w83637hg Winbond Electronics Corp America, w83637hg Datasheet - Page 116

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w83637hg

Manufacturer Part Number
w83637hg
Description
Winbond Lpc I/o Lpc I/o
Manufacturer
Winbond Electronics Corp America
Datasheet

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8.3.3 Logical Device 2 (UART A)
CR30 (Default 0x01 if PNPCSV = 0 during POR, default 0x00 otherwise)
CR60, CR 61 (Default 0x03, 0xF8 if PNPCSV = 0 during POR, default 0x00, 0x00 otherwise)
These two registers select Serial Port 1 I/O base address [0x100:0xFF8] on 8 byte boundary.
CR70 (Default 0x04 if PNPCSV = 0 during POR, default 0x00 otherwise)
CRF0 (Default 0x00)
8.3.4 Logical Device 3 (UART B)
CR30 (Default 0x01 if PNPCSV = 0 during POR, default 0x00 otherwise)
CR60, CR 61 (Default 0x02, 0xF8 if PNPCSV = 0 during POR, default 0x00, 0x00 otherwise)
These two registers select Serial Port 2 I/O base address [0x100:0xFF8] on 8 byte boundary.
CR70 (Default 0x03 if PNPCSV = 0 during POR, default 0x00 otherwise)
Bit 7 - 1 : Reserved.
Bit 0
Bit 7 - 4 : Reserved.
Bit 3 - 0 : These bits select IRQ resource for Serial Port 1.
Bit 7 - 2 : Reserved.
Bit 1 - 0 : SUACLKB1, SUACLKB0
Bit 7 - 1 : Reserved.
Bit 0
Bit 7 - 4 : Reserved.
Bit [3:0] : These bits select IRQ resource for Serial Port 2.
= 1 Activates the logical device.
= 0 Logical device is inactive.
= 00
= 01
= 10
= 11
= 1 Activates the logical device.
= 0 Logical device is inactive.
UART A clock source is 1.8462 Mhz (24MHz/13)
UART A clock source is 2 Mhz (24MHz/12)
UART A clock source is 24 Mhz (24MHz/1)
UART A clock source is 14.769 Mhz (24 MHz/1.625)
- 111 -
Publication Release Date: March, 2006
W83637HF/HG
Revision 1.6

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