w83628g Winbond Electronics Corp America, w83628g Datasheet - Page 8

• Manufacturer Part Number: w83628g
• Description: Pci-to-isa Bridge , Kit With W83629d.
• Manufacturer: Winbond Electronics Corp America

7. PIN DESCRIPTION
Note: Please refer to Section 13.2 DC CHARACTERISTICS for details.
I/O 12t
I/O 24t
I/O 12tp3
I/O 24tp3
I/OD 12t
I/O 24t
OUT 12t
OUT 24t
OUT 12tp3
OUT 24tp3
OD 12
OD 24
IN cs
IN t
IN td
IN ts
IN tsp3
7.1 W83628F PIN DESCRIPTION
7.1.1 PCI Interface
AD[31:0]
C/BE[3:0]#
PCICLK
PCLK_OUT
SYMBOL
- TTL level bi-directional pin with 12 mA source-sink capability
- TTL level bi-directional pin with 24 mA source-sink capability
- 3.3V TTL level bi-directional pin with 12 mA source-sink capability
- 3.3V TTL level bi-directional pin with 24 mA source-sink capability
- TTL level bi-directional pin open drain output with 12 mA sink capability
- TTL level bi-directional pin with 24 mA source-sink capability
- TTL level output pin with 12 mA source-sink capability
- TTL level output pin with 24 mA source-sink capability
- 3.3V TTL level output pin with 12 mA source-sink capability
- 3.3V TTL level output pin with 24 mA source-sink capability
- Open-drain output pin with 12 mA sink capability
- Open-drain output pin with 24 mA sink capability
- CMOS level Schmitt-trigger input pin
- TTL level input pin
- TTL level input pin with internal pull down resistor
- TTL level Schmitt-trigger input pin
- 3.3V TTL level Schmitt-trigger input pin
19-26
30-37
52-59
61-63
66-70
28,45
51,60
PIN
47
48
I/O 24tp3
I/O 24tp3
OUT
I/O
IN t
12t
PCI Bus Address and Data Signals. The standard PCI address
and data lines. Address is driven with FRAME# assertion, data is
driven or received in following clocks.
PCI Bus Command and Byte Enables. During the address
phase of a transaction C/BE[3:0]# define the bus command.
During the data phase C/BE[3:0]# are used as Byte Enables.
PCI Bus System Clock. PCICLK provides timing for all
transactions on the PCI bus. All other PCI signals are sampled
on the rising edge of PCICLK, and all timing parameters are
defined with respect to this edge.
PCI Bus System Clock DPLL Output. The PCLK_OUT can
reduce the PCICLK Loading and it produced from internal DPLL.
-8-
W83628F & W83629D
FUNCTION