w83627ef Winbond Electronics Corp America, w83627ef Datasheet - Page 124

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w83627ef

Manufacturer Part Number
w83627ef
Description
Lpc Super I/o For Desktop & Server
Manufacturer
Winbond Electronics Corp America
Datasheet
CR E5h. (Reserved)
CR E6h. (Default 1Ch)
2~1
BIT
7~0
BIT
7
6
5
4
3
0
Reserved.
R / W-Clear
READ / WRITE
Reserved.
READ / WRITE
R / W
R / W
R / W
R / W
R / W
ENMDAT =>
3 keys (ENMDAT_UP, CRE6[7]; MSRKEY, CRE0[4]; MSXKEY, CRE0[1])
define the combinations of the mouse wake-up events. Please check out
the table in CRE0[4] for the detailed.
CASEOPEN Clear Control.
Write 1 to this bit will clear CASEOPEN status.
cleared, please write 0 after event be cleared. The function is as same as
Index 46h bit 7 of H/W Monitor part.
Power loss Last State Flag. (VBAT)
0: ON
1: OFF.
PWROK_DEL (first stage)
Set the delay rising time from PWROK_LP to PWROK_ST.
0: 300 ~ 600 ms.
1: 200 ~ 300 ms.
PWROK_DEL
Set the delay rising time from PWROK_ST to POWEROK.
00: No delay time.
10: 96 ms
PWROK_TRIG =>
Write 1 to re-trigger POWEROK signals from low to high.
(VSB)
(VSB)
W83627EHF/EF, W83627EHG/EG
- 118 -
(VSB)
(VSB)
DESCRIPTION
DESCRIPTION
01: Delay 32 ms
11: Delay 250 ms
This bit won’t be self

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