MK1491 Integrated Circuit System, MK1491 Datasheet - Page 4

• Manufacturer Part Number: MK1491
• Description: Geodeclock Chip
• Manufacturer: Integrated Circuit System

MDS 1491-06 F
Power Down Control Table
External Components
The MK1491-06 requires some inexpensive external components for proper operation. Decoupling capacitors of 0.1µF should be
connected on each VDD pin to ground, as close to the MK1491-06 as possible. A series termination resistor of 33
each clock output. See the discussion below for other external resistors required for proper I/O operation. The 14.3 MHz oscillator
has internal caps that provide the proper load for a parallel resonant crystal with C L =18 pF. For tuning with other values of C L , the
formula 2*(C L -18) gives the value of each capacitor that should be connected between X1 and ground and X2 and ground.
The MK1491-06 provides more functionality in a 28 pin package by using
a unique I/O technique. The device checks the status of all I/O pins
during power-up and at exit from the Power Down state. This status
(pulled high, low, or mid-level) then determines the frequency selections
and power down modes (see the tables on pages 2 and 4). Within 10ms
after power up, the inputs change to outputs and the clocks start up. In the
diagrams to the right, the 33
termination resistors. The 10k
zero. Weak internal pull-up resistors are present on SEL24, EPCI#, FS,
LE#, PCISTP#, and SLOW#. These pins should be connected directly to
VDD or GND if not under active control. Internal resistors on PEN, SEL
AUDIO, and TS pull to a mid-level (M).
Key: 1 = connected to VDD, 0 = connected to ground, X = any valid logic level, Combination Input/Outputs should be connected to VDD or
Ground through a 10 k resistor as shown below.
I/O Structure
Power-On Default Conditions
PCISTP# PWRDWN# SLOW#
Input Pin#
X
0
1
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA • 95126 • [phone]tel • www.icst.com
10
12
13
15
16
21
22
28
5
8
0
1
1
SEL AUDIO
PWRDWN#
PCISTP#
Function
SLOW#
EPCI#
SEL24
PEN
LE#
TS
FS
X
X
X
Power Down
PCI STOP
Default Condition
MODE
resistor pulls low to generate a logic
ON
M
M
M
1
1
1
1
1
1
1
resistors are the normal output
All outputs enabled.
Audio clock (pin 28) set to 24.576 MHz
PCI clocks set to 33.3 MHz. Refer to Power Down Control Table above.
PCI frequency = 33.3 MHz.
24M/14.3M (pin 19) set to 24 MHz.
All clocks running.
PCI clocks running.
Low EMI function OFF
Pin 22 set to normal PCI signal (not early).
PCI (pin 25) set to PCI clock (33.33 MHz). PCI (pin 24) set to PCIF clock (33.33 MHz).
LOW
LOW
PCI
ON
LOW
PCIF
ON
ON
4
24/14.3 14.3 DESCRIPTION
LOW
ON
ON
CS5530 Geode
LOW All outputs low. PLLs and Oscillator off.
ON PCI clocks synchronously enter and leave low state.
ON All Clocks On.
*Note: Do not use a TTL load. This will
overcome the 10 k
input to a logic 1.
For select
= 0 (low)
Revision 101700
I/O
™
pulldown and force the
Clock Source
10k
33
MK1491-06
Don’t stuff for
“1” selection
Printed 11/15/00
may be used for
to load*