tc5299j ETC-unknow, tc5299j Datasheet - Page 13

• Manufacturer Part Number: tc5299j
• Description: Fast Ethernet Pcmcia Controller
• Manufacturer: ETC-unknow

5 Configuration Registers
5.1 Configuration Register A
5.2 Configuration Register B
Name
LCIM
PS. EL: The bit only set on EEPROM loading.
Name
MIISEL[1:0]
IO16CON
FULL_CFG
LNK_CFG
FDUPLEX
PCMIOALL
FREAD
XX
To prevent any accidental writes of this register it is”hidden” behind a previously unused register. Register 0AH
in the Controller's Page 0 of registers was previously reserved on a read. Now Configuration Register A can be
read at that address and can be written to by following a read to 0AH with a write to 0AH. If any other Controller
register accesses take place between the read and the write then the write to 0AH will access the Remote Byte
Count Register 0.
To prevent any accidental writes of his register it is ”hidden” behind a previously unused register. Register 0BH in
the Controller's Page 0 of registers was previously reserved on a read. Now Configuration Register B can be read
at that address and can be written to by following a read to 0BH with a write to 0BH. If any other Controller
register accesses take place between the read and the write then the write to 0BH will access the Remote Byte
Count Register 1.
XX
7
XX
7
R/W
FREAD
R/W
R/W
R/W
R/W
R/W
R/W
EL
R/W
R
LINT
6
6
Description
10: Default value to active the MII bus.
Other: reserved.
When this bit is set high the Controller generates IO16* after REG* active. If low this
output is generated only on address decode.
The bit is described EXLEDF what the polarity is.
0: Low active/ Hi inactive
1: Hi active/ Low inactive
The bit is described EXLEDL what the polarity is.
0: Low active/ Hi inactive
1: Hi active/ Low inactive
The Full-Duplex setting bit.
1: Full-duplex mode,
0: Half-duplex mode
The bit is indicated the decode-number of SA[9:0].
0: Only decode 5 address-lines, SA[5:0].
1: Full decode 10 address-lines, SA[9:0].
The TC5299J Controller supports 4 words Remote DMA read/write cache. When this
bit is set high, Remote DMA cache control will be enabled.
Reserved
Description
The interrupt mask bit for link status changed. When set to “1”, the Interrupt will
generate on link status changed
FDUPLEX
EXTRMII
5
5
LNK_CFG FULL_CFG IO16CON
MIICINT
4
4
-13-
.
3
MIICIM
3
LINK
2
2
LCINT
MIISEL1
1
1
LCIM
0
MIISEL0
0
07/04/01
Ver. 0.1
TC5299J