ncn6804 ON Semiconductor, ncn6804 Datasheet - Page 12

• Manufacturer Part Number: ncn6804
• Description: Dual Smart Card Interface Ic With Spi Programming Interface
• Manufacturer: ON Semiconductor

10. Card A: b5 = 0, Card B: b5 = 1, Device # 1: b6 = 0 ⇔ pin S1 connected to GND, Device # 2: b6 = 1 ⇔ pin S1 connected to V
11. Address 101 and bits [b0:b4] not documented in the table are not applicable with no effect on the device programming and configuration.
Read Register ³ READ_REG
from the card interface. The selected chip register is
transferred to the MISO Pin during the MOSI sequence
(CS = Low).
content of READ_REG is transferred on the MISO line
When a command is sent to A for example by selecting the
address %000 the corresponding MISO byte has the state of
the interface A (Card detectA, b4; I/OA, b3; C4A, b2; C8A,
b1; CRD_VCCA ok, b0) – that is the state loaded while
sending the previous MOSI command A or B.
When a command is sent to B for example by selecting the
address %001 the corresponding MISO byte has the state of
the interface B (Card detectB, b4; I/OB, b3; C4B, b2; C8B,
b1; CRD_VCCB ok, b0) – that is the state loaded while
sending the previous MOSI command A or B.
Card A or Card B Selection - Multiplexed Mode
the NCN6804's interface A or B (see Table 2) to the
exception of the addresses {100} decoded with no effect on
the device and {101} used to program device general
configuration. Then:
Table 3. MOSI AND MISO BITS IDENTIFICATIONS AND FUNCTIONS
Table 2. WRT_REG BIT DEFINITIONS AND FUNCTIONS
b7
MOSI
MISO
The READ_REG register (1 byte) contains the data read
Table 3 gives a definition of the bits.
Depending upon the programmed SPI_MODE, the
The bit b5 in the MOSI sequence enables the selection of
0
0
0
0
1
1
1
1
1
1
1
The sign X in the table means that either 1 or 0 can be used.
.
ADRESS
b6
S1
S1
S1
S1
1
0
0
0
0
0
0
b7
0
0
0
0
1
1
z
A/B
A/B
A/B
A/B
A/B
b5
1
1
1
1
1
1
MSB0
b6
0
0
1
1
1
1
z
CRD_RST
CRD_RST
CRD_RST
CRD_RST
CRD_RST
b5
0
1
0
1
0
1
z
b4
X
X
X
X
X
X
Card Detect
CRD_RST
CRD_RST
CRD_RST
CRD_RST
CRD_RST
CRD_RST
b4
CRD_CLK
b3
X
X
X
X
X
X
0
0
1
1
CRD_CLK
CRD_CLK
CRD_CLK
CRD_CLK
CRD_CLK
CRD_CLK
CRD_I/O
b3
CRD_I/O
b2
0
1
0
1
0
0
0
0
1
1
http://onsemi.com
CRD_CLK
CRD_CLK
CRD_CLK
CRD_CLK
CRD_I/O
CRD_I/O
CRD_C4
NCN6804
b2
LSB0
CRD_C4
12
b1
0
0
1
1
0
0
1
1
0
0
PARAMETERS
either on the Positive going (SPI_MODE = Special) or upon
the Negative going slope (SPI_MODE = Normal) of the
CLK_SPI signal.
bits since they carry no valid data.
When b5 = LOW the interface A is selected and the
transaction or communication takes place through this
interface according to Table 2. The programming applies to
Card A only.
When b5 = HIGH the interface B is selected and the
transaction or communication takes place through this
interface according to Table 1. The programming applies to
Card B only.
applied to card A when the device is switched from A to B.
This mode of operating is of course the same when the
device is switched from B to A: CRD_VCCB and
CRD_CLKB can be maintained applied to card B.
address {101} similarly to the NCN6001. In that case, the
programming is applied simultaneously to Card A and
Card B.
CRD_VCC
CRD_VCC
CRD_VCC
CRD_VCC
CRD_C4
CRD_C4
CRD_C8
The external microcontroller shall discard the three high
CRD_VCCA and CRD_CLKA can be maintained
The device configuration is programmed using the
b1
CRD_C8
b0
0
1
0
1
0
1
0
1
0
1
PWR Monitor
CRD_VCC
CRD_VCC
CRD_VCC
CRD_VCC
CRD_C8
CRD_C8
b0
MOSI bits[
CRD_CLK
b3 : b2]
Low
1/1
1/2
1/4
Async. Card A, Program Chip
Async. Card B, Program Chip
Async. Card A, Program Chip
Async. Card B, Program Chip
Sync. Card A, Sets Card Bits
Sync. Card B, Sets Card Bits
MOSI bits
CRD_VCC
[b1 : b0 ]
Operating Mode
Read Back Data
1.8V
3.0V
5.0V
0
Synchronous
MOSI bits
[b3 : b0 ]
SLO_SLP
FST_SLP
Special
Normal
DD
NO
NC