qlx4600-s30 Intersil Corporation, qlx4600-s30 Datasheet - Page 4

• Manufacturer Part Number: qlx4600-s30
• Description: Quad Lane Extender
• Manufacturer: Intersil Corporation

Pin Descriptions
PIN NAME
CP2[C,B,A]
CP1[C,B,A]
OUT2[N,P]
OUT1[N,P]
EXPOSED
BGREF
ENB
PAD
CLK
PIN NUMBER
39, 40, 41
42, 43, 44
33, 34
36, 37
38
45
46
-
4
Equalizer 2 differential output, CML. The use of 100nF low ESL/ESR MLCC capacitor with at least
4GHz frequency response is recommended.
Equalizer 1 differential output, CML. The use of 100nF low ESL/ESR MLCC capacitor with at least
4GHz frequency response is recommended.
External bandgap reference resistor. Recommended value of 6.04kΩ ±1%.
Control pins for setting equalizer 2. CMOS logic inputs. Pins are read as a 3-digit number to set
the boost level. A is the MSB, and C is the LSB. Pins are internally pulled down through a 25kΩ
resistor.
Control pins for setting equalizer 1. CMOS logic inputs. Pins are read as a 3-digit number to set
the boost level. A is the MSB, and C is the LSB. Pins are internally pulled down through a 25kΩ
resistor.
Serial data enable (active low), CMOS logic. Internal registers can be programmed with DI and
CLK pins only when the ENB pin is ‘LOW’. Internally pulled down.
Serial data clock, CMOS logic. Synchronous clock for serial data on DI and DO pins. Data on DI
is latched on the rising clock edge. Clock speed is recommended to be between 10MHz and
20MHz. Internally pulled down.
Exposed ground pad. For proper electrical and thermal performance, this pad should be
connected to the PCB ground plane.
(Continued)
QLx4600-S30
DESCRIPTION
November 19, 2009
FN6979.1