lm4312 National Semiconductor Corporation, lm4312 Datasheet - Page 2

• Manufacturer Part Number: lm4312
• Description: Mobile Pixel Link Two Mpl-2 , Rgb Display Differential Interface Serializer With Optional Dithering And Look Up Table
• Manufacturer: National Semiconductor Corporation

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MPL-2 SERIAL BUS PINS
SPI INTERFACE and CONFIGURATION PINS
VIDEO INTERFACE PINS
POWER/GROUND PINS
Pin Descriptions
Note:
I = Input, O = Output, IO = Input/Output. Do not float unused input pins.
DD0P, DD0M,
DD1P, DD1M
DCP, DCM
Pin Name
SPI_CSX
SPI_SCL
SPI_DO
SPI_DI
R[7:0]
G[7:0]
RES1
PCLK
B[7:0]
PD*
V
V
TM
HS
DE
VS
DD
SS
of Pins
No.
24
4
2
1
1
1
1
1
1
1
1
1
1
1
7
1
Power Supply Power Supply Pins. All VDD pins must be connect to power supply.
O, MPL-2
O, MPL-2
I/O, Type
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
Ground
O,
I,
I,
I,
I,
I,
I,
I,
I,
I,
I,
I
MPL-2 Differential Data Line Driver True (Plus) and Compliment (Minus) Outputs
Channel 0 and 1
MPL-2 Differential Clock Line Driver True (Plus) and Compliment (Minus) Outputs
SPI_Chip Select Input
SPI port is enabled when: SPI_CSX is Low, PD* is High.
SPI_Clock Input
SPI Data Input
SPI Data Output
Power Down Mode Input
PD* = Low, SER is in SLEEP Mode,
SPI Registers are RESET, LUT Data is retained.
PD* = High and PCLK = Stopped, SER is in SLEEP Mode,
SPI Register settings are retained and LUT data is retained.
PD* = High, Device is enabled.
Tie High
Tie Low
H = Test Mode (Reserved)
Pixel Clock Input
Video Signals are latched on the RISING edge.
RGB Data Bus Inputs – Bit 7 is the MSB.
24-bit Mode - use RGB[7:0]
18-bit Mode - use RGB[7:2], tie off RGB[1:0] to GND, do not float.
Vertical Sync. Input
This signal is used as a frame start for the Dither block and is required when
Dither option is selected.
The VS signal is serialized unmodified.
Horizontal Sync. Input
Data Enable Input
1.6V to 2.0V
Ground Pin
DAP pad must be connected to Ground.
2
RGB Serializer
Description