lm2512 National Semiconductor Corporation, lm2512 Datasheet - Page 16

• Manufacturer Part Number: lm2512
• Description: Mobile Pixel Link Level 0, 24-bit Rgb Display Interface Serializer With Dithering And Look Up Table Option
• Manufacturer: National Semiconductor Corporation

www.national.com
Power Up Sequence
The MPL Link must be powered up and enabled in a certain
sequence for proper operation of the link and devices. The
following list provides the recommended sequence:
1.
2.
3.
4.
A typical connection diagram is shown in Figure 18. The
LM2512 SPI is configured to support write only transactions
in this example. The FPD95120 can support both writes and
reads on its SPI interface. Figure 19 shows a typical power
up sequence using the shared SPI interface. Power is brought
up first. The RST_N signal is held low until power to the
FPD95120 (not shown) and the LM2512 is stable and within
specifications. Next the RST_N signal is driven High, which
allows access to the SPI interfaces. The PCLK should also
be turned on and held at a static level (High or Low). The
FPD95120 is selected first via a write to register 16’h (see
FPD95120 datasheet) and the display is initialized. Next a
write of FF’h to register 16’h. This command will Lock the
FPD95120 SPI interface and Select / Unlock the LM2512 SPI
Apply Power (See Power Supply Section)
PD* Input should be held low until Power is stable and
within specification and PCLK is driven to a static level.
PD* is driven HIGH, SPI interface is now available.
To program the device via the SPI interface:
— Select / Unlock the LM2512, Write FF’h to REG 16’h
FIGURE 18. Typical Application Connection Diagram
FIGURE 19. Power Up Sequence
16
5.
6.
interface. By default, the LM2512 powers up in 3 MD lanes
with the LUT disabled. The Look-up Table - LUT is accessible
by enabling bit 0 of the command register 00’h. The Special
Register Access - SRA are also accessible for lane scaling by
enabling bit 4 of the command register 00’h. To enable the
LUT and unlock SRA, write of 11’h to register 00’h (See
LM2512 SPI Register Table). To change to 2 MD lanes, write
of 02’h to register 0A’h. The LM2512 has the potential to pow-
er-up into a condition which causes unwanted leakage current
in the SRAMs. An access to each SRAM over the SPI inter-
face as part of the power-up sequence is recommended in
order to eliminate a potential power-up current leakage. Write
of XX’h (don’t care) data value or address value to each of the
three SRAM registers (03’h, 05’h and 07’h). Next additional
— LUT registers are now accessible
— If Lane Scale Register need to be modified, this is
— A write to REG 16’h on any other value besides FF’h
— SPI Commands MUST be completed before the
Condition the DES as required
Start PCLK, after the DES is calibrated and the SER PLL
Locked, streaming data transmission will occur.
accessed through bit 4 of the Command register.
will de-select / lock the LM2512’s SPI
PCLK is active.
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