lm25117psqx National Semiconductor Corporation, lm25117psqx Datasheet - Page 3

• Manufacturer Part Number: lm25117psqx
• Description: Wide Input Range Synchronous Buck Controller With Analog Current Monitor
• Manufacturer: National Semiconductor Corporation

TSSOP
Pin Descriptions
Pin
10
11
12
13
14
15
16
17
1
2
3
4
5
6
7
8
9
LLP
Pin
24
10
11
12
13
14
15
16
18
1
2
3
4
5
7
8
9
VCCDIS Optional input that disables the internal VCC regulator. If VCCDIS>1.25V, the internal VCC regulator
DEMB
AGND
COMP
RAMP
PGND
Name
UVLO
RES
CSG
VCC
CM
SW
CS
SS
RT
FB
LO
Description
Under-voltage lockout programming pin. If the UVLO pin voltage is below 0.4V, the regulator is in the
shutdown mode with all functions disabled. If the UVLO pin voltage is greater than 0.4V and less than
1.25V, the regulator is in standby mode with the VCC regulator operational, the SS pin grounded, and
no switching at the HO and LO outputs. If the UVLO pin voltage is above 1.25V, the SS pin is allowed
to ramp and pulse width modulated gate drive signals are delivered to the HO and LO pins. A 20μA
current source is enabled when UVLO exceeds 1.25V and flows through the external UVLO resistors
to provide hysteresis.
Optional logic input that enables diode emulation when in the low state. In diode emulation mode, the
low-side NMOS is latched off for the remainder of the PWM cycle after detecting reverse current flow
(current flow from output to ground through the low-side NMOS). When DEMB is high, diode emulation
is disabled allowing current to flow in either direction through the low-side NMOS. A 50kΩ pull-down
resistor internal to the LM25117 holds DEMB pin low and enables diode emulation if the pin is left
floating.
The restart timer pin that configures the hiccup mode current limiting. A capacitor on the RES pin
determines the time the controller remains off before automatically restarting. The hiccup mode
commences when the controller experiences 256 consecutive PWM cycles of cycle-by-cycle current
limiting. After this occurs, an 10μA current source charges the RES pin capacitor to the 1.25V threshold
and restarts LM25117.
An external capacitor and an internal 10μA current source set the ramp rate of the error amplifier
reference during soft-start. The SS pin is held low when VCC< 4V, UVLO < 1.25V or during thermal
shutdown.
The internal oscillator is programmed with a single resistor between RT and the AGND. The
recommended maximum oscillator frequency is 750kHz. The internal oscillator can be synchronized
to an external clock by coupling a positive pulse into the RT pin through a small coupling capacitor.
Analog ground. Return for the internal 0.8V voltage reference and analog circuits.
is disabled. VCCDIS has an internal 500kΩ pull-down resistor to enable the VCC regulator when the
pin is left floating. The internal 500kΩ pull-down resistor can be overridden by pulling VCCDIS above
1.25V with a resistor divider connected to an external bias supply.
Feedback. Inverting input of the internal error amplifier. A resistor divider from the output to this pin
sets the output voltage level. The regulation threshold at the FB pin is 0.8V.
Output of the internal error amplifier. The loop compensation network should be connected between
this pin and the FB pin.
Current monitor output. Average of the sensed inductor current is provided. Monitor directly between
CM and AGND. CM should be left floating when the pin is not used.
PWM ramp signal. An external resistor and capacitor connected between the SW pin, the RAMP pin
and the AGND pin sets the PWM ramp slope. Proper selection of component values produces a RAMP
signal that emulates the AC component of the inductor with a slope proportional to input supply voltage.
Current sense amplifier input. Connect to the high-side of the current sense resistor.
Kelvin ground connection to the current sense resistor. Connect directly to the low-side of the current
sense resistor.
Power ground return pin for low-side NMOS gate driver. Connect directly to the low-side of the current
sense resistor.
Low-side NMOS gate drive output. Connect to the gate of the low-side synchronous NMOS transistor
through a short, low inductance path.
Bias supply pin. Locally decouple to PGND using a low ESR/ESL capacitor located as close to
controller as possible.
Switching node of the buck regulator. Connect to the bootstrap capacitor, the source terminal of the
high-side NMOS transistor and the drain terminal of the low-side NMOS through a short, low
inductance path.
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