cs7410 Cirrus Logic, Inc., cs7410 Datasheet - Page 27

• Manufacturer Part Number: cs7410
• Description: Cd/mp3/wma Audio Controller
• Manufacturer: Cirrus Logic, Inc.

4.4
DS553PP3
defaults to a 7-bit value of 0x1B. A second serial controller (SER2) supports industry standard 3-wire and
4-wire protocols. In master mode, this interface can control a front panel or a small non-volatile memory. In
slave mode, it can operate under control of an external processor, for example, in a combination unit. The
third serial port (SER3) is a 5-wire master device optimized for reading CD subcodes from the servo chip,
and can also be used a general-purpose serial port.
SDRAM / DRAM Interface
These pins are used to interface the CS7410 with external synchronous or EDO DRAMs. Data widths of 4
to 16 bits are supported. The CS7410 supports word or block transfers (partial word transfers are not re-
quired).
gives pin definitions for interfacing to EDO DRAM.
3, 4, 5, 6, 7, 8, 9,
10, 11, 13, 15, 20,
21, 22, 23, 24
25, 26, 27, 28,
29, 30, 31, 32,
33, 34, 35, 36
Pin
60
61
65
66
67
68
69
70
72
74
76
Table 10
Pin
SER1_CLK
SER1_DAT
SER2_CLK
SER3_CLK
SER3_SS0
SER3_SS1
37
39
41
SER2_DO
SER2_CS
SER3_DO
SER2_DI
SER3_DI
Signal
Name
gives instructions on how to interface to any particular configuration of SDRAM.
Address[11..0]
Signal Name
DR_RAS_L
DR_CAS_L
Type
Data[15..0]
M_WE_L
O
O
O
O
B
B
B
B
B
I
I
DRAM
DRAM
Debug port serial clock
Debug port serial data
Clock for 4-wire serial port (output for master mode, input for slave mode)
Input data for 4-wire serial port
Output data for 4-wire serial port – may function as bidirectional data in 3-
wire mode.
Chip select for 4-wire serial port (output if master, input if slave mode).
Can also be used as bidirectional ready line.
Clock output
Data output – up to 32 bits per transfer.
Data input – up to 96 bits per transfer.
Slave select for first peripheral (programmable polarity)
Slave select for second peripheral (programmable polarity)
Type
Table 9. Serial Interface Pins
Table 10. SDRAM Interface
O
O
O
O
B
Memory Data Bus.
Memory Address Bus. Connect in order starting with
DR_Addr[0] to all RAM address pins not already con-
nected to DR_BS_L or DR_AP.
Memory Row Address Strobe
Memory Column Address Strobe
Memory Write Enable
Description
Description
CS7410
Table 11
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