rdc19220 ETC-unknow, rdc19220 Datasheet - Page 13

• Manufacturer Part Number: rdc19220
• Description: 16-bit Monolithic Tracking Resolver Lvdt -to-digital Converters
• Manufacturer: ETC-unknow

tor to an inverting integrator with a 50 pF nominal feedback capac-
itor. When it integrates to -1.25 V, the converter counts up 1 LSB
and when it integrates to +1.25 V, the converter counts down 1
LSB. When a count is taken, a charge is dumped on the capaci
VELOCITY TRIMMING
RDC-19220 Series specifications for velocity scaling, reversal
error and offset are contained in TABLE 1. Velocity scaling and
offset are externally trimmable for applications requiring tighter
specifications than those available from the standard unit. FIG-
URE 10 shows the setup for trimming these parameters with
external pots. It should also be noted that when the resolution is
changed, VEL scaling is also changed. Since the VEL output is
from an integrator with capacitor feedback, the VEL voltage can-
not change instantaneously. Therefore, when changing resolu-
tion while moving there will be a transient with a magnitude pro-
portional to the velocity and a duration determined by the con-
verter bandwidth.
INCREASED TRACKING/DECREASED SETTLING
(GEAR SHIFTING)
Connecting the BIT output to the resolution control lines (A and
B) will change the resolution of the converter down (“gear shift”)
and make the converter settle faster and track at higher rates.
The converter bandwidth is independent of the resolution.
ADDITIONAL ERROR SOURCES
Quadrature voltages in a resolver or synchro are by definition the
resulting 90° fundamental signal in the nulled out error voltage (e)
in the converter. This voltage is due to capacitive or inductive cou-
pling in the synchro or resolver signals. A digital position error will
result due to the interaction of this quadrature voltage and a refer-
ence phase shift between the converter signal and reference
inputs. The magnitude of this error is given in the following formula:
Where:
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Magnitude of Error = (Quadrature Voltage/F.S.signal) • tan
RDC-19220
FIGURE 10. VELOCITY TRIMMING
-VCO
VEL
100 R
0.4 R (SCALING)
0.8 R
V
V
V
+5 V
-5 V
100 kΩ
(OFFSET)
13
An example of the magnitude of error is as follows:
Then: Magnitude of Error = 0.36 min @ 1 LSB in the 16th bit.
Note: Quadrature is composed of static quadrature which is
Where:
PHASE SHIFT COMPENSATION
FIGURE 11 illustrates a circuit to LEAD or LAG the reference
into the converter that will compensate for phase-shift between
tan
Where
X
Where f = carrier frequency
Where c = capacitance
c
Magnitude of Error is in radians
Quadrature Voltage is in volts
Full Scale signal is in volts
Let: Quadrature Voltage = 11.8 mV
Let: F.S. signal = 11.8 V
Let:
Speed Voltage = (rotational speed/carrier frequency) • F.S. signal
Speed Voltage is the quadrature due to rotation.
or resolver.
Carrier frequency is the REF in Hz.
Rotation speed is the rps (rotations per second) of the synchro
=
= signal to REF phase shift
specified by the synchro or resolver supplier plus the speed
voltage which is determined by the following formula:
2 fc
=
FIGURE 11. PHASE-SHIFT COMPENSATION
1
= 6°
X
R
= desired phase-shift
c
+ REF
+ REF
- REF
- REF
R
C
LEAD
LAG
R
C
+ REF
- REF
+ REF
- REF
RDC-19220 SERIES
R-12/05-0