x96010 Intersil Corporation, x96010 Datasheet - Page 12
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x96010
Manufacturer Part Number
x96010
Description
Sensor Conditioner With Dual Look Up Table Memory And Dacs
Manufacturer
Intersil Corporation
Datasheet
1.X96010.pdf
(26 pages)
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
x96010V14IZ
Manufacturer:
IDT
Quantity:
989
I2DS: C
(N
The I2DS bit sets the polarity of Current Generator 2,
DAC2. When this bit is set to “0” (default), the Current
Generator 2 of the X96010 is configured as a Current
Source. Current Generator 2 is configured as a Cur-
rent Sink when the I2DS bit is set to “1”. See Figure 7.
Control Register 1
This register is accessed by performing a Read or Write
operation to address 81h of memory. This byte’s volatility
is determined by bit NV1234 in Control register 0.
L1DA5 - L1DA0: LUT1 D
When bit L1DAS (bit 4 in Control register 5) is set to
“1”, LUT1 is addressed by these six bits, and it is not
addressed by the output of the on-chip A/D converter.
When bit L1DAS is set to “0”, these six bits are ignored
by the X96010. See Figure 9.
A value between 00h (00
ten to these register bits, to select the corresponding row
in LUT1. The written value is added to the base address
of LUT1 (90h).
Control Register 2
This register is accessed by performing a read or write
operation to address 82h of memory. This byte’s vola-
tility is determined by bit NV1234 in Control register 0.
L2DA5 - L2DA0: LUT2 D
When bit L2DAS (bit 6 in Control register 5) is set to
“1”, LUT2 is addressed by these six bits, and it is not
addressed by the output of the on-chip A/D converter.
When bit L2DAS is set to “0”, these six bits are ignored
by the X96010. See Figure 9.
A value between 00h (00
ten to these register bits, to select the corresponding row
in LUT2. The written value is added to the base address
of LUT2 (D0h).
ON
-
VOLATILE
URRENT
)
G
ENERATOR
10
10
IRECT
IRECT
12
) and 3Fh (63
) and 3Fh (63
2 D
A
A
IRECTION
CCESS
CCESS
10
10
) may be writ-
) may be writ-
B
B
S
ITS
ITS
ELECT
B
IT
X96010
Control Register 3
This register is accessed by performing a Read or Write
operation to address 83h of memory. This byte’s volatility
is determined by bit NV1234 in Control register 0.
D1DA7 - D1DA0: D/A 1 D
When bit D1DAS (bit 5 in Control register 5) is set to
“1”, the input to the D/A converter 1 is the content of
bits D1DA7 - D1DA0, and it is not a row of LUT1.
When bit D1DAS is set to “0” (default) these eight bits
are ignored by the X96010. See Figure 8.
Control Register 4
This register is accessed by performing a Read or Write
operation to address 84h of memory. This byte’s volatil-
ity is determined by bit NV1234 in Control register 0.
D2DA7 - D2DA0: D/A 2 D
When bit D2DAS (bit 7 in Control register 5) is set to
“1”, the input to the D/A converter 1 is the content of
bits D2DA7 - D2DA0, and it is not a row of LUT2.
When bit D2DAS is set to “0” (default) these eight bits
are ignored by the X96010. (See Figure 8).
Control Register 5
This register is accessed by performing a Read or
Write operation to address 85h of memory.
L1DAS: LUT1 D
VOLATILE
When bit L1DAS is set to “0” (default), LUT1 is
addressed by the output of the on-chip A/D converter.
When bit L1DAS is set to “1”, LUT1 is addressed by
bits L1DA5 - L1DA0.
D1DAS: D/A 1 D
VOLATILE
When bit D1DAS is set to “0” (default), the input to the
D/A converter 1 is a row of LUT1. When bit D1DAS is set
to “1”, that input is the content of the Control register 3.
)
)
IRECT
IRECT
A
A
CCESS
CCESS
IRECT
IRECT
S
A
A
S
ELECT
CCESS
CCESS
ELECT
B
B
B
B
IT
October 25, 2005
IT
ITS
ITS
(N
(N
ON
FN8214.1
ON
-
-