qt60160 Quantum Research Group, qt60160 Datasheet - Page 15

• Manufacturer Part Number: qt60160
• Description: 16 And 24 Key Qmatrix Touch Sensor Ics Research Group
• Manufacturer: Quantum Research Group

5 I
5.1 Interface Bus
More detailed information about I
www.i2C-bus.org. Devices are connected onto the I
shown in Figure 5.1. Both bus lines are connected to V dd via
pull-up resistors. The bus drivers of all I
open-drain type. This implements a wired-AND function which
allows any and all devices to drive the bus, one at a time. A
low level on the bus is generated when a device outputs a
zero.
5.2 Transferring Data Bits
Each data bit transferred on the bus is accompanied by a
pulse on the clock line. The level of the data line must be
stable when the clock line is high; The only exception to this
rule is for generating START and STOP conditions.

Parameter
Address space
Maximum bus speed (SCL)
Hold time START condition
Setup time for STOP condition
Bus free time between a STOP and START
condition
SDA
SCL
SDA
SCL
2
C Operation
Device 1
Table 5.1 I
Figure 5.1 I
Figure 5.2 Data Transfer
Device 2
Data Stable
2
C Bus Specifications
Device 3
2
Data Change
C Interface Bus
2
C is available from
Device n
Data Stable
2
C devices must be
Vcc
Unit
7-bit
100 kHz
4µs minimum
4µs minimum
4.7µs minimum
R1
2
C bus as
R2
15
5.3 START and STOP Conditions
The host initiates and terminates a data transmission. The
transmission is initiated when the host issues a START
condition on the bus, and is terminated when the host issues
a STOP condition. Between START and STOP conditions, the
bus is considered busy. As shown below, START and STOP
conditions are signaled by changing the level of the SDA line
when the SCL line is high.
5.4 Address Packet Format
All address packets are 9 bits long, consisting of 7 address
bits, one READ/WRITE control bit and an acknowledge bit. If
the READ/WRITE bit is set, a read operation is performed,
otherwise a write operation is performed. When the device
recognizes that it is being addressed, it will acknowledge by
pulling SDA low in the ninth SCL (ACK) cycle. An address
packet consisting of a slave address and a READ or a
WRITE bit is called SLA+R or SLA+W, respectively.
The most significant bit of the address byte is transmitted
first. The address sent by the host must be consistent with
that selected with the option jumpers.
5.5 Data Packet Format
All data packets are 9 bits long, consisting of one data byte
and an acknowledge bit. During a data transfer, the host
generates the clock and the START and STOP conditions,
while the Receiver is responsible for acknowledging the
reception. An acknowledge (ACK) is signaled by the Receiver
pulling the SDA line low during the ninth SCL cycle. If the
Receiver leaves the SDA line high, a NACK is signaled.
SDA
SCL
START
Figure 5.3 START and STOP Conditions
Figure 5.4 Address Packet Format
SDA
SCL
Addr MSB
START
1
2
QT60240-ISG R8.06/0906
Addr LSB
7
STOP
R/W
8
ACK
9