lmf90 National Semiconductor Corporation, lmf90 Datasheet - Page 12

• Manufacturer Part Number: lmf90
• Description: 4th-order Elliptic Notch Filter
• Manufacturer: National Semiconductor Corporation

V
GND
2 0 Applications Information
2 2 PROGRAMMING PINS
The LMF90 has five control pins that are used to program
the filter’s characteristics via a three-level logic scheme In
dual-supply applications these inputs are tied to either V
V
tics For example the W input (pin 1) sets the filter’s pass-
band width to 0 55 f
connected to V
and GND to the D input (pin 10) will set the notch depth to
40 dB or 30 dB respectively
The R input (pin 2) is another three-level logic input and it
sets the clock-to-center-frequency ratio to 33 33 1 50 1 or
100 1 for input voltages equal to V
tively Note that the clock frequency referred to here is the
frequency at the CLK pin and at the frequency divider output
(if used) This is different from the frequency at the divider’s
input LD (pin 3) sets the frequency divider’s division factor
to either 716 596 or 2 for input voltages equal to V
or V
crystal oscillator and clock divider When XLS is connected
to the positive supply the oscillator and divider are enabled
and CLK is the output of the divider and can drive the clock
inputs of other LMF90s When XLS is connected to GND
the oscillator and divider are disabled and the CLK pin be-
comes a clock input for CMOS-level signals Connecting
XLS to the negative supply disables the oscillator and divid-
er and causes CLK to operate as a TTL-level clock input
Using an external 3 579545 MHz color television crystal with
the internal oscillator and divider it is possible to build a
power line frequency notch for 50 Hz or 60 Hz line frequen-
cies or their second and third harmonics using the LMF90 A
60 Hz notch is shown in the Typical Application circuit on
the first page of this data sheet Connecting LD to V
changes the notch frequency to 50 Hz Changing the clock-
to-center-frequency ratio to 50 1 results in a second-har-
monic notch and a 33 1 ratio causes the LMF90 to notch
the third harmonic
Table I illustrates 18 different combinations of filter band-
width depth and clock-to-center-frequency ratio obtained
by choosing the appropriate W D and R programming volt-
ages
b
b
D
or GND in order to select a particular set of characteris-
b
R
respectively XLS (pin 7) enables and disables the
TABLE I Operation of LMF90 Programming Pins Values given are for nominal levels of attenuation
GND
V
GND
V
V
V
W
a
a
b
b
a
GND or V
0
A
(dB)
b
b
b
b
b
b
0 26 f
min
30
30
30
35
40
40
V
0
b
or 0 127 f
b
(f
BW f
CLK
0 12
0 26
0 55
0 12
0 26
0 55
respectively Applying V
a
f
0
GND or V
0
0
e
when the W input is
100)
SBW f
0 019
0 040
0 082
0 010
0 024
0 050
(Continued)
b
a
0
respec-
GND
a
b
a
A
b
b
b
b
b
b
(dB)
min
30
30
30
35
40
40
12
GND (f
2 3 DIGITAL INPUTS AND OUTPUTS
As mentioned above the CLK pin can serve as either an
input or an output depending on the programming voltage
on XLS When CLK is operating as a TTL input it will oper-
ate properly in both dual-supply and single-supply applica-
tions because it has two logic thresholds one referred to
V
CLK swings rail-to-rail (CMOS logic levels)
XTAL1 and XTAL2 are the input and output pins for the
internal crystal oscillator When using the internal oscillator
(XLS connected to V
these two pins When the internal oscillator is not used
XTAL2 should be left open XTAL1 can be used as an input
for an external CMOS-level clock signal swinging from V
to V
applied to XTAL1 will be divided by the internal frequency
divider as determined by programming voltage on the LD
pin
2 4 SAMPLED-DATA SYSTEM CONSIDERATIONS
OUTPUT STEPS
Because the LMF90 uses switched-capacitor techniques its
performance differs in several ways from non-sampled (con-
tinuous) circuits The analog signal at the input to the inter-
nal bandpass filter (pin 12) is sampled during each clock
cycle and since the output voltage can change only once
every clock cycle the result is a discontinuous output signal
The bandpass output takes the form of a series of voltage
‘‘steps’’ as shown in Figure 3 The steps are smaller when
the clock frequency is much greater than the signal frequen-
cy
Switched-capacitor techniques are used to set the summing
amplifier’s gain Its input and feedback ‘‘resistors’’ are actu-
ally made from switches and capacitors Two sets of these
‘‘resistors’’ are alternated during each clock cycle Each
time these gain-setting components are switched there will
be no feedback connected to the op amp for a short period
of time (about 50 ns) This generates very low-amplitude
output signals at f
The amplitude of each of these intermodulation compo-
nents will typically be at least 70 dB below the input signal
amplitude and well beyond the spectrum of interest
b
BW f
0 12
0 26
0 55
0 12
0 26
0 55
CLK
and one referred to GND When operating as an output
a
0
The frequency of the crystal or the external clock
f
0
e
50)
SBW f
0 019
0 040
0 082
0 010
0 024
0 050
CLK
0
a
a
) the crystal is connected between
f
IN
A
(dB)
b
b
b
b
b
b
f
min
CLK
30
30
30
35
40
40
V
a
b
(f
f
IN
CLK
BW f
0 12
0 26
0 55
0 12
0 26
0 55
2 f
f
CLK
0
0
e
a
33 33)
SBW f
f
IN
0 019
0 040
0 082
0 010
0 024
0 050
etc
b
0