lmf60 National Semiconductor Corporation, lmf60 Datasheet - Page 10

• Manufacturer Part Number: lmf60
• Description: High Performance 6th-order Switched Capacitor Butterworth Lowpass Filter
• Manufacturer: National Semiconductor Corporation

http
1 0 LMF60 Application Hints
The LMF60 is comprised of a non-inverting unity gain low-
pass sixth-order Butterworth switched capacitor filter sec-
tion and two undedicated CMOS Op-Amps The switched-
capacitor topology makes the cutoff frequency (where the
gain drops 3 01 dB below the DC gain) a direct ratio (100 1
or 50 1) of the clock frequency supplied to the lowpass filter
Internal integrator time constants set the filter’s cutoff fre-
quency The resistive element of these integrators is actual-
ly a capacitor which is ‘‘switched’’ at the clock frequency
(for a detailed discussion see Input Impedance section)
Varying the clock frequency changes the value of this resis-
tive element and thus the time constant of the integrators
The clock to cutoff frequency ratio (f
ratio of the input and feedback capacitors in the integrators
The higher the clock to cutoff frequency ratio (or the sam-
pling rate) the closer the approximation is to the theoretical
Butterworth response The LMF60 is available in f
ratios of 50 1 (LMF60-50) or 100 1 (LMF60-100)
1 1 CLOCK INPUTS
The LMF60 has a Schmitt-trigger inverting buffer which can
be used to construct a simple R C oscillator The oscillator
www national com
CLK
FIGURE 1 Schmitt Trigger R C Oscillator
f
C
) is set by the
CLK
f
C
10
frequency is dependent on the buffer’s threshold levels as
well as on the resistor capacitor tolerance (See Figure 1 )
Schmitt-trigger threshold voltage levels can vary significant-
ly causing the R C oscillator’s frequency to vary greatly
from part to part
Where accuracy in f
used to drive the CLK R input of the LMF60 This input is
TTL logic level compatible and also presents a very light
load to the external clock source ( E 2 mA) with split sup-
plies and L Sh tied to system ground The logic level is pro-
grammed by the voltage applied to level shift (L Sh) pin (See
the Pin Description for L Sh pin)
1 2 POWER SUPPLY BIASING
The LMF60 can be biased from a single supply or dual split
supplies The split supply mode shown in Figures 2 and 3 is
the most flexible and easiest to implement As discussed
earlier split supplies
TTL or CMOS clock logic levels Figure 4 shows two
schemes for single supply biasing In this mode only CMOS
clock logic levels can be used
TL H 9294 – 8
C
f
Typically for V
f
CLK
CLK
g
is required an external clock can be
2V to
e
e
RC In
1 37 RC
1
g
CC
7V will enable the use of

V
V
e
CC
CC
V
b
b
1
a
V
V
b
T
T
b
a
V
J
b
V
V
e
T
T
a
b
10V
(