th7301 ETC-unknow, th7301 Datasheet - Page 4

• Manufacturer Part Number: th7301
• Description: Dual-channel Programmable Low-pass Filter
• Manufacturer: ETC-unknow

TH7301 Dual-Channel Programmable Low-Pass Filter
Serial Interface
Programming
Operating
conditions
for the 3 wire
interface
The serial interface is a 3-wire bus used to
program the filter cutoff frequency and voltage
gain. Pin SDATA is the serial data input for an 8-
bit shift register, SCLK is the shift register clock
(active positive edge), SDEN (active high) is the
serial interface enable. Note that logic levels are
Figure 3: Serial Interface Timing Diagram
The serial data is stored in one of 3 internal
registers - gain control, frequency select A and
frequency select B.
The first two bits of the serial data form an
address code for the registers. The gain control
bits AC(5...0) are decoded to select a voltage gain
between 0 dB and 20.5 dB in 0.5 dB steps. The
frequency select bits FC(2...0) select one of the
octave chords while FS(6...0) select the step
within each chord.
Parameter
Power supply voltage
High level input voltage
Low level input voltage
Serial data clock period
Serial data setup time
Serial data hold time
Serial data enable delay time
Serial data enable hold time
Notes:
Frequency Select A
Frequency Select B
Gain Control
Logic threshold levels for inputs SCLK, SDATA and SDEN. Note that this is a negative supply IC.
Usage
Symbol
tDEN
tHEN
tCLK
VSS
tHD
VIH
VIL
tSD
Address Bits
D7
0
0
1
VSS - 0.1V
0.3 * VSS
-5.25
Min
D6
50
10
10
20
20
0
1
1
OS0
AC5
FS2
D5
referenced to a - 5 V supply and that there is no
global reset for the logic devices, so a reset word
should be input after power up.
The timing diagram for the interface is shown
below.
Additional bit OS0 (active high) controls the
oscillator (for test issues only). The table below
shows the address and data decoding of the serial
data input.
The serial interface does not contain a power on
reset, thus all three registers must be pro-
grammed after power on to prevent undefined
logical states and to achieve reliable filter opera-
tion. I. e. a first reset word may reset all registers
to 0.
Typ
-5.0
FS1
AC4
D4
0
VDD + 0.1V
0.7 * VSS
-4.75
Max
AC3
FS0
FS6
D3
Data Bits
FC2
AC2
FS5
Unit
D2
ns
ns
ns
ns
ns
V
AC1
FC1
FS4
D1
relative to VDD
Comments
note
note
FC0
FS3
AC0
D0
4