mc44871 Freescale Semiconductor, Inc, mc44871 Datasheet - Page 9

• Manufacturer Part Number: mc44871
• Description: Tuning Circuit With High Speed Tuning Supply
• Manufacturer: Freescale Semiconductor, Inc

Bit T13: Switches the Band Buffer Output to Test Mode
F ref is the reference frequency. F by2 is the output frequency of
the programmable divider divided–by–2.
Bit T14: Controls the Charge Pump Current
Bit AD2, AD1, AD0: Indicate the ADC Pin Analog Level
Bit LO: Indicates the Status of Lock Detetector
V CC = 5.0 V
MOTOROLA ANALOG IC DEVICE DATA
I B + I SUB = 5.5 mA Typical
I B = Base Current
I SUB = Substrate Current of PNP
In the test mode, B2 and B1 have to be ON (B2=B1=1).
T13 = 0
T14 = 0
LO = 0
LO = 1
Figure 6. Equivalent Circuit of the Integrated
Figure 7. Equivalent Circuit of the Integrated
= 1
= 1
ADC Input Voltage
“On”/“Off”
0.18 to 0.34 V CC
0.66 to 0.82 V CC
”On”/”Off”
0.34 to 0.5 V CC
0.5 to 0.66 V CC
0.82 to 1.0 V CC
0 to 0.18 V CC
I B1
I B2
I B3
I B
Normal Operation
Test Mode: F ref Out at B2 F by2 Out at B1
Pump Current 5.0 A
Pump Current 20 A
PLL Status Not Locked
PLL Status Locked
PNP Band Buffers
NPN Band Buffer
200
Protection 20...25 V
I B1 + I B2 + I B3 = 0.5 mA Typ
I B = Base Current
I SUB
B0 B2
AD2
0
0
0
0
1
1
Out
V CC
Saturation Voltage
0.2 V Typical
0.5 V Max
AD1
30 mA (40 mA
at 0 to 80 C)
0
0
1
1
0
0
1.2 V typ
@ 5.0 mA
Out B4
AD0
0
1
0
1
0
1
MC44871
OPERATING DESCRIPTION
Introduction
application are shown in Figures 1 and 8. A discussion of the
features and function of each of the internal blocks is given.
The Programmable Divider
When it has counted to zero it takes its required division ratio
out of the latches B. Latches B are loaded from latches A by
means of signal TDI which is synchronous to the
programmable divider output signal.
programmable divider; this double latch scheme is needed to
assure correct data transfer to the counter.
N = 16384 x N14 + 8192 x N13 +
programmable divider is set to a counting ratio of N = 256 or
higher.
The Prescaler
guarantees high input sensitivity.
The Phase Comparator
sensitive and has very low output leakage current in the high
impedance state.
The Operational Amplifier
low input bias current and high power supply rejection. The
positive input is biased internally. The operational amplifier
output (Pin 1) needs an external 750 k pull–up resistor (560
k
pump output current capability.
The Oscillator
in series with a capacitor. The crystal operates in the series
resonance mode.
distortion.
Power Dissipation
200 mW (V TUN = 15 V with external pull–up of 560 k , one
buffer “On” at 30 mA). It is calculated with the following
formula:
A representative block diagram and typical system
The programmable divider is a presettable down counter.
Since latches A receive the data asynchronously with the
The division ratio definition is given by:
Maximum Ratio 32767
N0
At power–on the whole bus receiver is reset and the
The divide–by–8 prescaler has a preamplifier which
The phase comparator is both phase and frequency
The operational amplifier is designed for very low noise,
The oscillator uses a 3.2 or a 4.0 MHz crystal tied to ground
The voltage at Pin 15 has low amplitude and low harmonic
The typical power dissipation of the circuit is about
minimum). This minimum value is defined by the charge
PD
N14 are the different bits for frequency information.
+
Example: (5 x 38)
V
)
CC
)
(0.20 x 30)
x I
V sat x I
CC
)
Out
Minimum Ratio 256
+
V
)
Pin2
197 mW
buffer
5.6 x 10 5
560 k
+ 4 x N2 + 2 x N1 + N0
32 – 15
*
V
W
TUN
x 15
x V
TUN
9