toim5232 Vishay, toim5232 Datasheet - Page 11

• Manufacturer Part Number: toim5232
• Description: Sir Endec For Irda? Applications Integrated Interface Circuit
• Manufacturer: Vishay

in figure 7 and figure 8. The difference is just the time scale.
It also indicates the delay of the decoded channel 2 vs.
channel 1.
“ECHO-ON” OR “ECHO-OFF” AND “LATENCY ALLOWANCE”
During transmission, the receiver inside a transceiver
package is exposed to very strong irradiance of the
transmitter, which causes overload conditions in the receiver
circuit. After transmission it takes some time to recover from
this condition and return to the specified sensitivity.
During this time the receiver is in an unstable condition, and
at the output unexpected signals may arise. Also, during
transmission under overload conditions the receiver may
show signals on the RXD channel that are similar to or
identical with the transmitted signal. To get clean or at least
specified conditions for the receive channel during
transmission, different terms were defined. The time to allow
the receiver to recover from overload conditions is the
latency allowance or shorter, just the specified latency. This
is covered by the IrDA physical layer specification and is a
maximum of 10 ms. IrDA specifies shorter negotiable
latency. In SIR the minimum is 0.5 ms. This includes
software latency. Transceivers are in general below 0.3 ms.
In the first generations, some suppliers did not care for the
behavior of the RXD output of the transceivers during
transmission and latency time. The software is able to handle
Document Number: 81749
Rev. 1.2, 17-Nov-10
1->
2->
3->
21036
CON9
Fig. 9 - Data reception with the setting 115.2 kbit/s
J1
1
6
2
7
3
8
4
9
5
External input
3.6V max.
1) Ch1: TOIM4232; RD_IR, pin 15, vertical scale: 2 V/div.,
2) Ch2: TOIM4232; RD_232, pin 3
3) Ch3: TOIM4232; RD_LED, pin 10
horizontal scale: 10 µs/div.
RXD
TXD
Vcc
C3
C4
+
+
RTS (BR/D)
DTR (RESET)
CON2
11
10
12
J2
1
3
5
9
1
2
C+
C1-
C2+
C2-
T1IN
T2IN
R1OUT
R2OUT
Fig. 10 - Demo Board Circuit with Echo-Suppression to be Used for Echo-On and Echo-Off Transceivers.
MAX3232
Z1
U1
C1
T1OUT
T2OUT
[e-mail], [e-mail],
R1IN
R2IN
VCC
+ C2
V+
V-
16
2
6
15
14
7
13
8
For technical questions within your region, please contact one of the following:
+
C6
+
R1
C5
+
C7
Z2
SIR Endec for IrDA
C8
Y1
R2
Integrated Interface Circuit
1
2
3
4
5
6
7
8
RESET
BR/D
RD_232
TD_232
Vcc_SD
X1
X2
GND
C9
TOIM4232*)
*) For TOIM5232 pinning, see figure 1.
U2
RD_LED
TD_LED
RD_IR
TD_IR
Vcc
NC
S2
S1
16
15
14
13
12
11
10
9
®
Channel 1 shows the signal from the transceiver. In this case
it is TFDU4100 with unsymmetrical switching times.
TFDU4100 (obsolete) used an open collector output with an
internal load resistor. That caused a slow trailing edge (but
fast enough for all applications). The later generations are
using tri-state outputs with push-pull drivers with symmetrical
pulse switching times. All Vishay IrDA transceivers exhibit
constant output pulse duration in SIR mode of about 2 µs
independent of the duration of the optical input pulse.
that. The easiest way is to clean up the receiver channel after
sending the last pulse and waiting for the latency period.
Later, many transceivers that block the RXD channel during
transmission and during the latency period were released to
the market. This behavior is called “Echo-off”. Unfortunately,
some OEMs like to use the signal from the RXD channel
during transmission, as a self-test feature for testing the
device on board without using the optical domain. Therefore,
many new devices have been developed to echo the TXD
input signal at the RXD output. Such behavior is called
“echo-on”.
Some software developed for “echo-off” applications is not
able to receive and understand the signals from echo-on
devices correctly.
Therefore, an add-on to the circuit shown in figure 1 was
generated to suppress the echo from the receiver during
transmission. This modification is shown in figure 10.
During transmission, the signal from the RXD output of the
transceiver is just gated by the transmit signal, (see the
oscilloscope picture in figure 11).
Applications
R5
1
5
7
NC_1
NO_2
INS1
8
DG2039
V+
U4
[e-mail]
COM_1
COM_2
4
INS2
D
2
6
3
C10
C11
+
R3
This line not used forTFDU4101
2
4
6
8
Vishay Semiconductors
TFDU4300
TFDU4101
Cathode
RXD
Vcc1
GND
Pin7: TFDU4101:NC
TFDU4300:Vlog
U3
21047
Anode
TXD
SD
.
1
3
5
7
optional
R4
TOIM5232
www.vishay.com
11