mc13883 Freescale Semiconductor, Inc, mc13883 Datasheet
mc13883
Available stocks
Related parts for mc13883
mc13883 Summary of contents
Page 1
... Introduction The MC13883 integrated charger, USB on-the-go transceiver, and carkit interface incorporates support for the CEA-936-A carkit specification. The MC13883 provides charging from a variety of sources, USB connectivity (including on-the-go, OTG), as well as support for phone-powered accessories. The MC13883 is an “all in one” IC that integrates nearly the entire interface, Li-Ion battery charging, and transceiver circuitry required to support these functions ...
Page 2
... Detectors VUSB SE1 SPI/I2C DETECTOR Interface VUSB S h USB XCVR e DGND AGND Figure 1. Block Diagram MC13883 Technical Data, Rev. 3 BATTP VBUS VUSB VC BG_BYP INT to processor RESETB IO_REG VCCIO SPI _ MOSI _ I2CADR1 SPI _ MISO _I2C_SDA to/ from SPI _ CLK _I2C_SCL ...
Page 3
... Specifically, the MC13883 allows the phone to be charged from a PC via a USB port. While this is a very useful feature from an end-user perspective feature that adds some additional requirements to the bus due to the unique limitations and requirements the USB specification places on devices that are attached to a USB port. The MC13883 simplifies the task of identifying whether “ ...
Page 4
... Data and audio signaling modes share the same DP (Data Plus) and DM (Data Minus) pins of the mini-USB connector. The phone transitions between the four types of signaling modes using Signaling Negotiation Protocol (SNP) described in the CEA-936-A Carkit specification. The MC13883 bus supports both 4-wire and 5-wire protocols. ...
Page 5
... Table 1. Pin Descriptions (continued) Description Block USB USB USB USB USB USB/Charger Charger GND Charger Control Charger Bandgap Charger Charger Control SPI/I2C MC13883 Technical Data, Rev. 3 Signal Descriptions I/O Supply Type I/O Analog Output Analog Input VC Digital Input VCCIO Digital Input VCCIO Digital Output Analog ...
Page 6
... Electrical Characteristics 3 Electrical Characteristics 3.1 Absolute Maximum Ratings Table 2 shows the absolute maximum voltage and temperature ratings of the MC13883 IC. Operation outside the limits shown may cause damage to the device and negatively affect performance. Parameter VBUS, CHRGCTRL, BPFET, PATH_SEL Voltage Rating All GNDs ...
Page 7
... Active Mode Idle Mode Off Mode 4 Power Architecture 4.1 Power Architecture Overview The MC13883 IC contains the following power-related features: • Single and dual-path charging from USB connector • Fully compliant with USB, USB OTG, enhanced mini-USB, and CEA-936-A specifications • Over-voltage protection • ...
Page 8
... Voltage Regulator and Switching Logic CHRGMODE CHRGCTRL ISENSE ICHRG BP_FET To A/D Convertor Input Back-to-Back FET FET Figure 2. Power Architecture Block Diagram MC13883 Technical Data, Rev. 3 VUSB VUSB LDO Seamless/ FET Switching Logic BP BATT_FET PWR_ON BATTP Turnon signal Battery Battery FET ...
Page 9
... D1 and M4 to the B+ node, (BP pin). (B+ is the main phone supply node from which most other internal phone power rails are derived, MC13883 pin BP is attached to it.) The basic supply path when a charger is not attached to the phone is from the battery through M3 to B+. ...
Page 10
... Batt Voltage Regulator OC + with Current Comp + Limit and - OC_ - OV Curr Out REF Protection Diff Amp Voltage Error Amp Table MC13883 Technical Data, Rev. 3 Table 0.1 Ω Turnon Signal to Phone PWR_ON BP BATT_FET FET Switching Ctrl Logic FET_CTRL Voltage BP_FET_BIT Error Amp BATT_FET_BIT ...
Page 11
... Curr Out REF Protection Diff Amp Voltage Error Amp Table Table 5. FET Combinations M1 M2 Si8401 Si8401 Si8415 Si8401 FDZ293P FDZ293P MC13883 Technical Data, Rev. 3 Power Architecture Rs B+ 0.1 Ω Turnon Signal to Phone PWR_ON BP BATT_FET BATTP FET Switching Ctrl Logic FET_CTRL Voltage BP_FET_BIT ...
Page 12
... The BATTPON threshold is the threshold above which the phone will turn on while charging in either single-path mode or with a USB charger in serial- or dual-path mode. CHRG_CURR (Internal Signal) The CHRG_CURR threshold and is used as part of charger detection For dual-path, CHRGMODE should be grounded. C MC13883 Technical Data, Rev. 3 Freescale Semiconductor ...
Page 13
... Freescale Semiconductor Description Min Typ Low to High 3.33 3.43 50 Low to High 3.70 High to Low 3.50 50 High to Low 10 20 0.2 Table 7 for dual path, Table 8 for serial path and MC13883 Technical Data, Rev. 3 Power Architecture Max Unit 3.53 Volts 200 mV 3.90 Volts 3.75 Volts Table 9 for single 13 ...
Page 14
... ON H *ICHRG bits X >BATTPON ON H *ICHRG bits X X OFF L OFF MC13883 Technical Data, Rev. 3 Description Trickle PWR_ Charge ON Signal OFF L USB Host Attach. Limited activation current, Open BP_FET, open BATT_FET OFF L USB Host Attach. Limited activation current, Open BP_FET, open BATT_FET ...
Page 15
... X <BATTPON H Full Rate *ICHRG_TR X >BATTPON H Full Rate *ICHRG_TR OFF MC13883 Technical Data, Rev. 3 Power Architecture Description Trickle PWR_ON Charge Signal OFF L USB Host Attach. Limited activation current, Open BP_FET, open BATT_FET OFF L USB Host Attach. Limited activation current, Open BP_FET, open BATT_FET ...
Page 16
... X <BATTPON N/A ***100/300/ 600 mA X >BATTPON N/A ***100/300/ 600 N/A OFF MC13883 Technical Data, Rev. 3 Description PWR_ON Signal N/A L USB Host Attach. Limited activation current, Open BP_FET, open BATT_FET N/A L USB Host Attach. Limited activation current, Open BP_FET, open BATT_FET N/A L USB Host Attach. Limited activation current, ...
Page 17
... If both the Charge Regulator and Reverse mode are disabled, the ICHRG pin outputs a voltage that is proportional to the ID pin. In idle mode, the MC13883 IC draws extra current when the MUX associated with the ICHRG pin is enabled. This extra current is significant enough that standby time will be affected. To disable drive to this pin, the ID_ICHRG_MUX_ENB can be asserted as listed in Bit 4 ...
Page 18
... Over-voltage Protection There are three paths in the MC13883 IC that are protected from an over-voltage event: through the two external paths present in dual path charging as well as an internal path from VBUS to the USB section of the IC. When an over-voltage condition is sensed at the VBUS pin, all 3 paths are opened. This is accomplished by driving the CHRGCTRL and BP_FET pins high while opening the internal path ...
Page 19
... Following RVRS_CHRG_INT being set by the hardware, the software needs to wait for at least this amount of time before enabling RVRS_MODE path. Table 41, then the RVRS_MODE path will be turned MC13883 Technical Data, Rev. 3 Power Architecture Min Typ Max Units μA 2 ...
Page 20
... A 1111 Fully On - Disallow battery FET to be turned on in hardware Figure 3, Figure MC13883 Technical Data, Rev. 3 Table 13. This current is max 0 85 213 320 390 488 585 6835 781 878 976 1073 1170 ...
Page 21
... ICHRG_TR[2:0] 4.2.11 Standalone Trickle Charging MC13883 has a standalone trickle charge mode of operation in order to ensure that a completely discharged battery can be charged without the microprocessor’s control. This is especially important in single path configurations and when charging from a USB host. Upon plugging a valid USB Host to the phone in Dual Path or Serial Path mode, the trickle cycle is started at a current of TRICKLEL and remains at this level until charging is terminated ...
Page 22
... CHRGCTRL. For charging, it has the capability of regulating to a fixed voltage. • It requires an output capacitor of 10 µF on both BP and BATTP pins. • Output voltage sensing is done at the ISENSE pin. 22 ICHRG[3:0]=0001 ICHRG[3:0]=0011 ICHRG[3:0]=0110 Min Typ Max -3% 2.7 +3% -3% 3.43 +3% -3% 3.7 +3% MC13883 Technical Data, Rev Units Freescale Semiconductor ...
Page 23
... VBUS to CHRGCTRL Voltage Batt = 3.6V VBUS = 4.1V ICHRG ≠0000 Charge path is OPEN Freescale Semiconductor Table 17. VCHRG Output Voltage Settings Battery Regulator Output Value 000 001 010 011 100 101 110 111 Condition Nom –-5% MC13883 Technical Data, Rev. 3 Power Architecture Voltage (V) 4.05 4.375 4.15 4.20 4.25 4.30 3.80 4.50 Min Typ Max ...
Page 24
... PWR_ON Output Low VBUS < CHRGDET threshold 4.2.14 VC Regulator and Bandgap The VC regulator is the MC13883’s internal regulator. It gets powered by the BP or VBUS. It powers the bandgap. VC powers much of the ICs’ internal functions. No external loading BG_BYP is allowed. Table 20. VC and Bandgap Performance Specifications ...
Page 25
... Section 4.2.1, “Dual-Path Charging Overview”, and Section 4.2.3, “Single-Path Table 6 in Section 4.2.4, “Charger Block Signal Logic” supports this section. When a USB power MC13883 Technical Data, Rev. 3 Power Architecture Overview”, Charging”, the charging Description”) and the Table 46—Table 51, Register 03 - ...
Page 26
... CHRGLED Current 4.2.19 Factory Mode Operation Factory mode allows for the ability to power on the MC13883 through a USB cable without a battery being attached. Factory mode is entered while when VBUS is greater than the CHRGDET threshold and ID is greater than 3 this mode, the BP regulator is enabled without having an SE1 on D+ and D-. Therefore, power can be supplied to the system and the D+ and D- lines are kept free for normal USB transmission ...
Page 27
... Table 23. USB Switch Control SW1 Closed Open Open Open Value Function 0 output = 2.775 V 1 output = 3.30 V Table 25. Table 25. VUSB Performance Specifications Condition MC13883 Technical Data, Rev. 3 Power Architecture below. VUSB VUSB LDO SW2 SW3 Open Open Closed Open Open Closed Closed Open ...
Page 28
... Maximum output current (Imax) is 50mA in normal mode. The regulator has a controlled current limit of 200mA (nom). In addition to the normal mode of operation, the regulator has a secondary mode (selected by SPI control) in which the output current limit is 910 µA nominal. 28 Condition Min - - MC13883 Technical Data, Rev. 3 Typ Max Units - 200 ...
Page 29
... Imax V_dropout @ Imax Active Quiescent current 4.2.24 VC Generator The MC13883 has an internal voltage generator Vc. This voltage is used internally for a number of pull-up resistors and is also brought out to allow used for CHRGMODE selection µF capacitor must be connected to this pin. 5 Connectivity To support the MC13883 bus data signaling modes the MC13883 IC contains a USB OTG transceiver and the UART controller ...
Page 30
... V VBUS Detector Comparator Turn On Delay 0.8 V VBUS Detector Comparator Turn Off Threshold 30 4.4V VBUS_DET_4V4 - + 2.0V VBUS_DET_2V to Interrupt - Generator + 0.8V VBUS_DET_0V8 - + Figure 7. VBUS Detector Block Diagram Table 27. Conditions rising edge falling edge VBUS>2V to VBUS_DET_2V = 1 MC13883 Technical Data, Rev. 3 VBUS Min Max Unit 4.4 4.65 V 4 100 µs 1.6 2.0 V 1.6 2.0 V ...
Page 31
... Resistor to ground is connected to the ID pin (0. < ID < 0.77 * VC) – non-USB accessory is attached • ID pin is grounded (ID < 0.12 * VC) – type plug is attached; indicates that the MC13883 default OTG master (A-Device) • Voltage level on the ID pin is 3.3 V ±300 mV – factory mode The block diagram in ...
Page 32
... Each time the ID line changes its status the ID_INT interrupt is generated. When the VUSB regulator is disabled, the MC13883 needs to be able to detect at least ID interrupts generated by ID_FLOAT and ID_GND changing their status to 00, 01, or 10. In addition, the CHRGDETI interrupt needs to be detected while the VUSB regulator is disabled ...
Page 33
... USB suspend mode, DM and DP are individually read to see if an SE1 is or isn't present. 5.1.4 DP Pull-Up and DP/DM Pull-Down Resistors The MC13883 IC has integrated pull-up resistors on the DP line and pull-down resistors on the DP and DM lines (D+ and D-). These resistors can be switched in or out individually via control bits. The resistors’ implementation is shown in Figure ...
Page 34
... USB ECN for Pull-Up/Pull-Down Resistor. At power up, both pull-downs are switched out. A 2.5 MΩ (±1.5 MΩ) pull-down resistor on the DM line is connected by default and is automatically disconnected in mono and stereo audio modes (MC13883 MODE[2:0] of 100 or 101). ...
Page 35
... VBUS_PULSE_TMR[2:0] bits. When Freescale Semiconductor Condition Min 900 14.3 105 VBUS_70KPD_ENB = 0 VBUS_3KPD_EN = 0 REG_5V_EN = greater than this voltage 3 less than this voltage VBUS_70KPD_ENB = 1 1.5 VBUS_3KPD_EN = 1 REG_5V_EN = 0 MC13883 Technical Data, Rev. 3 Connectivity Typ Max Units Ω 3090 24.8 kΩ 150 195 kΩ 1 2.5 4.0 MΩ 40 ...
Page 36
... Signaling Modes The MC13883 bus supports four signaling modes: USB, UART, mono audio and stereo audio. In addition, two loopback modes are provided for testing purposes. test modes. Mode MODE 2:0 USB 000 UART1 001 UART2 010 36 REG_5V Status ...
Page 37
... USB Modes The MC13883 IC contains a USB OTG transceiver that is compliant with the USB 2.0 specification and the USB On-the-Go supplement. The transceiver supports a low speed mode of 1.5 Mbits/second and a full speed mode of 12 Mbit/s. The speed of the transceiver is selected by the FSENB bit. The phone detects the speed requested by the peripheral by reading the DP and DM voltages ...
Page 38
... Connectivity In order to support different USB interfaces, the MC13883 bus USB transceiver can be configured to operate in one of four different modes: • VP_VM bidirectional, also known as 4-wire mode (DET_SE0 = 0, BI_DI = 1) • VP_VM unidirectional (DET_SE0 = 0, BI_DI = 0) • DAT_SE0 bidirectional, also known as 3-wire mode (DET_SE0 = 1, BI_DI = 1) • ...
Page 39
... DAT_VP, SE0_VM, VP, VM, RCV (400 µA) DAT_VP, SE0_VM, VP, VM, RCV (400 µA) DP, DM (1.5 kΩ to 3.6 V) DP, DM (15 kΩ to GND) DP, DM |(DP)-(DM)| DP, DM DP, DM DP, DM MC13883 Technical Data, Rev. 3 Connectivity A Mode Description TXENB = 1 DP => => VM DP/DM => RCV DP => DAT_VP DM => SE0_VM DP/DM => ...
Page 40
... In order to meet the requirement for the USB driver output impedance to be between 28 Ω and 44 Ω (full speed), two external 22 Ω resistors will be placed in series with the DP and DM lines. The USB transceivers with output impedance different than the MC13883 one-chip transceiver will require different external resistors. ...
Page 41
... In UART mode, the VP and VM receive pins are active and can be used for detection of logic levels on DP and DM, often used in accessory detection. 5.2.3 Audio Modes and Loopback Modes The MC13883 bus supports mono and stereo audio modes in which audio signals are multiplexed on DP/DM lines as follows: • in mono audio mode (VUSB_EN = 1, VUSB0 = 0, MODE[2:0] = 100) the phone’s speaker left output is routed to DM and the microphone input is connected to DP • ...
Page 42
... IC will be routed through the audio switch and 22 ohm resistor to a high impedance speaker amplifier in the MC13883 audio accessory (the MC13883 headset will also have a built-in amplifier). The TX audio path will not be loaded because the audio signal from the accessory microphone will be routed through the audio switch and 22 ohm resistor to a high impedance audio path input in a power management IC ...
Page 43
... In 4-wire interface protocol, the phone signals the accessory to exit audio mode by injecting a positive pulse on the DM line. When the DM_PULSE bit is set high while the phone is in audio signaling mode, the MC13883 IC generates a pulse of width between 200 to 500 ns and amplitude greater than 2 addition, the DM_PULSE bit is automatically cleared. ...
Page 44
... Power-Up Control The MC13883 IC always powers up in USB mode (USB_EN must be pulled or wired high). The USB transceiver defaults to mode determined by the BOOTMODE pin. BOOTMODE is a “trinary” pin that can detect three different conditions: the pin is grounded, the pin is floating, or the pin is pulled high. Floating means it will be between 0 ...
Page 45
... Rdp_pu1 (0.9K - 1.575K) DP VREG LDO VREG USB XCVR EN Freescale Semiconductor SW1 SW2 SW3 EN VREG_EN 1 mSec DELAY from SPI Figure 13. Power-Up Control Circuit MC13883 Technical Data, Rev. 3 Connectivity from SPI 5V_IN VBUS BP BOOTMODE BOOTMODE Decoder DAT_SE0 BI_DI SPI Registers RESETB USB_CNTRL USB_EN 45 ...
Page 46
... Connectivity 5.4 Interrupt The MC13883 IC has interrupt generation capability. The following signals can generate an interrupt via the MC13883 INT line: • VBUS detector: — VBUS_DET_4V4 — VBUS_DET_2V — VBUS_DET_0V8 • Charge detector (CHRGDET_INT) • ID detector — ID_FLOAT — ID_GND • SE1 Detector (SE1_DET_INT) • ...
Page 47
... Debounce based on values in Table 12. no debounce no debounce MC13883 Technical Data, Rev. 3 Description Logic high indicates that the interrupt is from a low to high or a high to low transition of the VBUSDET_4V4, VBUSDET_2V, or VBUSDET_0V8 output of the VBUS Detector. Write a “1” to this location to clear the interrupt. ...
Page 48
... Serial Interface 6 Serial Interface The MC13883 IC contains one SPI interface port and one I2C port to allow processor access to the MC13883 resources. Four pins are shared for SPI and I2C signals. Also, their functions are listed in Table 42. The I2C_SPIF_SEL pin selects SPI or I2C mode as shown in ...
Page 49
... SPI sequence. SPI_CS t_clk SPI_CLK t_smosi t_hmosi SPI_MOSI SPI_MISO Freescale Semiconductor Min 1.65 - 0.8*VCCIO - 0.7*VCCIO t_sw t_sw Dead Bit CLK t_smiso Figure 14. SPI Timing Diagram MC13883 Technical Data, Rev. 3 Serial Interface Max Unit 2 0.3*VCCIO t_scs t_hcs t_cslh t_hmiso 49 ...
Page 50
... The MC13883 operates as a slave. It has a 7 bit device address of ‘00101xx’ with the ‘xx’ being determined by the state of SPI_CS_I2C_ADR0 and SPI_MOSI_I2C_ADR1 pins. These pins are used to avoid any conflicts with other I2C devices, and thus, the MC13883’ ...
Page 51
... An address packet contains a 5-bit register address and 3 null bits. First bit of packet 0 A data packet contains 8 data bits. It may be sent by the host or the MC13883. Because the MC13883 registers contain 24-data bits, three data packets are needed for one data transfer. First bit of packet ...
Page 52
... To terminate the transfer of host driven packets, the host follows the MC13883’s ACK with a Stop condition. The host can also issue a Start condition after the module's ACK if it wants to start a new data transfer. ...
Page 53
... The following examples show how to write and read data to and from the MC13883. The host initiates and terminates all communication. The host sends a master command packet after driving the start condition. The MC13883 will respond to the host if the master command packet contains the MC13883 device address ...
Page 54
... VBUSOV_INT is not masked 1 = VBUSOV_INT is masked RVRS_CHRG_INT is not masked 1 = RVRS_CHRG _INT is masked ID_INT is not masked 1 = ID_INT is masked SE1_INT is not masked 1 = SE1_INT is masked CC_CV _INT is not masked 1 = CC_CV _INT is masked MC13883 Technical Data, Rev. 3 Description Description Freescale Semiconductor ...
Page 55
... IC Revision Bit 1 R N/A IC Revision Bit 2 R N/A Status of the BATTPON comparator BATTP < BATTPON Threshold 1 = BATTP > BATTPON Threshold R N low DP logic state 1 = high DP logic state R N low DM logic state 1 = high DM logic state MC13883 Technical Data, Rev. 3 SPI/I2C Register Tables Description Description Table 28. Table 28. 55 ...
Page 56
... VUSB output is disabled (unless USB_EN pin is asserted high VUSB output is enabled (regardless of USB_EN pin ICHRG MUX disabled, the ICHRG pin is Hi ICHRG MUX enabled REG_5V output is disabled (unless VBUS_PULSE_TMR[2:0] <> REG_5V output is enabled (regardless of VBUS_PULSE_TMR[2:0]) MC13883 Technical Data, Rev. 3 Description Description Freescale Semiconductor ...
Page 57
... DP pull-up is not automatically connected when SE0 is detected 1 = variable DP pull-up is automatically connected when SE0 is detected R USB transceiver disabled if USB_EN is low or if USB_CNTRL = USB transceiver enabled if MC13883 MODE[2:0] = 000 and RESETB is high MC13883 Technical Data, Rev. 3 SPI/I2C Register Tables Description Description 57 ...
Page 58
... ID line not pulsed 1 = pulse to gnd on the ID line generated R pin pulled through 220K resistor 1 = 5ua current source connected between the ID pin and VUSB R line not pulsed positive pulse on the DM line generated MC13883 Technical Data, Rev. 3 Description Table 40. Freescale Semiconductor ...
Page 59
... Packaging Information Figure 24 shows the pinout for the MC13883. and provide package dimensions. VC BG_BYP GNDREF VCCIO ICHRG SPI_CS_I2CADR0 SPI_CLK_I2CSCL SPI_MOSI_I2CADR1 SPI_MISO_I2CSDA EMU_INT Freescale Semiconductor Figure 25 through EMU One Chip Pinout 40 1 GND/SUBS 10 11 Figure 24. MC13883 Pinout MC13883 Technical Data, Rev. 3 Packaging Information ...
Page 60
... Packaging Information Figure 25. Outline Dimensions for QFN-40, 6x6 mm 60 (Case Outline 1624-01, Issue O) MC13883 Technical Data, Rev. 3 Freescale Semiconductor ...
Page 61
... Figure 26. Outline Dimensions for QFN-40, 6x6 mm - Continued Freescale Semiconductor (Case Outline 1624-01, Issue O) MC13883 Technical Data, Rev. 3 Packaging Information 61 ...
Page 62
... Packaging Information Figure 27. Outline Dimensions for QFN-40, 6x6 mm - Continued 62 (Case Outline 1624-01, Issue O) MC13883 Technical Data, Rev. 3 Freescale Semiconductor ...
Page 63
... Updated text and added FET table Updated BATTP column Updated BATTP column Updated FET_OVRD, FET_CTRL, BATT_FET, BATTP, and Trickle Charge columns New Added VBUS to CHRGCTRL parameter Updated text Updated Table 53. Revision History Changed from Product Preview to Technical Data. MC13883 Technical Data, Rev. 3 Product Documentation Revision Revision 63 ...
Page 64
... P.O. Box 5405 Denver, Colorado 80217 1-800-521-6274 or 303-675-2140 Fax: 303-675-2150 LDCForFreescaleSemiconductor@hibbertgroup.com Document Number: MC13883 Rev. 3 02/2010 Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document ...