ata6603 ATMEL Corporation, ata6603 Datasheet - Page 121

• Manufacturer Part Number: ata6603
• Description: Microcontroller With Lin Transceiver, 5v Regulator And Watchdog
• Manufacturer: ATMEL Corporation

4.12.7
4921D–AUTO–08/07
Timer/Counter Timing Diagrams
At the very start of period 2 in
even though there is no Compare Match. The point of this transition is to guarantee symmetry
around BOTTOM. There are two cases that give a transition without Compare Match.
The Timer/Counter is a synchronous design and the timer clock (clk
clock enable signal in the following figures. The figures include information on when interrupt
flags are set.
shows the count sequence close to the MAX value in all modes other than phase correct PWM
mode.
Figure 4-34. Timer/Counter Timing Diagram, no Prescaling
Figure 4-35
Figure 4-35. Timer/Counter Timing Diagram, with Prescaler (f
• OCRnx changes its value from MAX, like in
• The timer starts counting from a value higher than the one in OCRnx, and for that reason
value is MAX the OCn pin value is the same as the result of a down-counting Compare
Match. To ensure symmetry around BOTTOM the OCnx value at MAX must correspond to
the result of an up-counting Compare Match.
misses the Compare Match and hence the OCnx change that would have happened on the
way up.
(clk
(clk
TCNTn
TCNTn
TOVn
TOVn
clk
clk
clk
I/O
I/O
clk
/8)
/1)
I/O
TN
TN
I/O
shows the same timing data, but with the prescaler enabled.
Figure 4-34
MAX - 1
MAX - 1
contains timing data for basic Timer/Counter operation. The figure
Figure 4-33 on page 120
MAX
MAX
Figure 4-33 on page
OCnx has a transition from high to low
ATA6602/ATA6603
BOTTOM
clk_I/O
BOTTOM
120. When the OCR0A
/8)
T0
) is therefore shown as a
BOTTOM + 1
BOTTOM + 1
121