ata6832c ATMEL Corporation, ata6832c Datasheet - Page 4

• Manufacturer Part Number: ata6832c
• Description: High Temperature Triple Half-bridge Driver With Spi And Pwm
• Manufacturer: ATMEL Corporation

3. Functional Description
3.1
Figure 3-1.
4
CLK
DO
CS
Serial Interface
DI
Atmel ATA6832C [Preliminary]
Data Transfer
0
SRR
TP
1
LS1
S1L
Data transfer starts with the falling edge of the CS signal. Data must appear at DI synchro-
nized to CLK and is accepted on the falling edge of the CLK signal. The LSB (bit 0, SRR) has
to be transferred first. Execution of new input data is enabled on the rising edge of the CS sig-
nal. When CS is high, pin DO is in tri-state condition. This output is enabled on the falling edge
of CS. Output data will change their state with the rising edge of CLK and stay stable until the
next rising edge of CLK appears. LSB (bit 0, TP) is transferred first.
Table 3-1.
2
HS1
S1H
Bit
10
11
12
13
14
15
0
1
2
3
4
5
6
7
8
9
3
LS2
S2L
Input Register
4
S2H
HS2
Input Data Protocol
SRR
OLD
OCS
HS1
HS2
HS3
PH1
PH2
PH3
LS1
LS2
LS3
PL1
PL2
PL3
SI
5
LS3
S3L
6
HS3
S3H
Function
Status register reset (high = reset; the bits PSF and OVL in the output
data register are set to low)
Controls output LS1 (high = switch output LS1 on)
Controls output HS1 (high = switch output HS1 on)
See LS1
See HS1
See LS1
See HS1
Output LS1 additionally controlled by PWM Input
Output HS1 additionally controlled by PWM Input
See PL1
See PH1
See PL1
See PH1
Open load detection (low = on)
Overcurrent shutdown (high = overcurrent shutdown is active)
Software inhibit; low = standby, high = normal operation (data transfer is
not affected by the standby function because the digital part is still
powered)
7
n. u.
nPL!
8
n. u.
PH1
9
n. u.
PL2
10
PH2
n. u.
11
n. u.
PL3
12
PH3
n. u.
13
OLD
OVL
14
INH
OCS
9216B–AUTO–06/11
15
PSF
SI