max2140 Maxim Integrated Products, Inc., max2140 Datasheet - Page 13

• Manufacturer Part Number: max2140
• Description: Max2140 Complete Sdars Receiver
• Manufacturer: Maxim Integrated Products, Inc.

I
This is the standard I
C6, C4, C2 (hex) dependent on the state of the I
pins, for a write-to-device operation and either C7, C5,
C3 (hex) for a read-from operation (again dependent
on the state of pins I
Write Operation:
The first byte is the device address plus the direction
bit (R/W = 0).
The second byte contains the internal address com-
mand of the first address to be accessed.
The third byte is written to the internal register directed
by the command address byte.
The following bytes (if any) are written into successive
internal registers.
The transfer lasts until stop conditions are encountered.
The MAX2140 acknowledges every byte transfer.
Read Operation:
When either address C3, C5, C7 is sent, the MAX2140
sends back first the status byte then the reserved byte.
See Table 5 and Table 6 for read/write register operations.
The MAX2140 EV kit can be used as a starting point for
layout. For best performance, take into consideration
power-supply issues, as well as the RF, LO, and IF layout.
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
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© 2005 Maxim Integrated Products
Table 5. Example: Write Registers 1 to 3 with 0E, D8, 26
Table 6. Example: Read from Status Registers (Sending an NACK Terminate Slave
Transmit Mode
2
C Register Map:
Device Address Write
(C2, C4, C6)
Device Address Write
(C2, C4, C6)
2
2
CA_).
C protocol. The first byte is either
ACK
ACK
I
2
C Functional Description
Register Address 00 ACK DATA 0E
Register Address 00 ACK DATA 0E
Layout Issues
Printed USA
2
CA_
Complete SDARS Receiver
To minimize coupling between different sections of the
IC, the ideal power-supply layout is a star configuration,
which has a large decoupling capacitor at a central
V
each going to a separate V
circuit. At the end of each trace is a bypass capacitor
with impedance to ground less than 1Ω at the frequen-
cy of interest. This arrangement provides local decou-
pling at each V
capacitor for a low-inductance ground connection.
The layout of a matching network can be very sensitive
to parasitic circuit elements. To minimize parasitic
inductance, keep all traces short and place compo-
nents as close to the IC as possible. To minimize para-
sitic capacitance, a cutout in the ground plane (and
any other planes) below the matching network compo-
nents can be used. On the high-impedance ports (e.g.,
IF inputs and outputs), keep traces short to minimize
shunt capacitance.
TRANSISTOR COUNT: 22,000
PROCESS: BiCMOS
For the latest package outline information, go to
www.maxim-ic.com/packages.
CC
is a registered trademark of Maxim Integrated Products, Inc.
ACK
ACK
node. The V
DATA D8
DATA D8
CC
CC
pin. Use at least one via per bypass
traces branch out from this node,
Package Information
Matching Network Layout
ACK
ACK
Power-Supply Layout
Chip Information
CC
DATA 26
DATA 26
node in the MAX2140
ACK
ACK
STOP
STOP