el9115 Intersil Corporation, el9115 Datasheet - Page 6

• Manufacturer Part Number: el9115
• Description: Triple Analog Video Delay Line
• Manufacturer: Intersil Corporation

Applications Information:
EL9115 is a triple analog delay line receiver that allows skew
compensation between any three high frequency signals.
This part compensates for time skew introduced by a typical
CAT-5 cable with differing electrical lengths on each pair.
The EL9115 can be independently programmed via SPI
interface in steps of 2ns up to 62ns total delay on each
channel while achieving over 80MHz bandwidth.
Figure 13 shows the EL9115 block diagram. The 3 analog
inputs are ground reference single ended signals. After the
signal is received, the delay is introduced by switching filter
blocks into the signal path. Each filter block is an all-pass
filter introducing 2ns delay. In additional to time delay, each
filter block also introduces some low pass filtering. As a
result, the bandwidth of the signal path decrease from
120MHz at 0ns delay setting to 80MHz at the maximum
delay setting as shown in the frequency response curve in
the typical performance curves section.
In addition to delay, the extra amplifiers in the signal path
also introduce offset voltage. The output offset voltage can
shift by 100mV for X2 high setting and 50mV for X2 low.
In operation, it is best to allocate the most delayed signal
0ns delay then increase the delay on the other channels to
bring them into line. This will result in the lowest power and
distortion solution to balancing delays.
6
10
8
2
4
9
6
G_in
R_in
B_in
SCLOCK
NSENABLE
SDATA
3
+
+
+
5
1
FIGURE 13. EL9115 BLOCK DIAGRAM
19
Delay Line
Delay Line
Delay Line
EL9115
[bottom plate]
17
Control Logic
C
18
Power Dissipation
As the delay setting increases additional filter blocks turn on
and insert into the signal path. For each 2ns of delay per
channel Vsp current increases by 0.9mA while Vsm does not
change significantly. Under the extreme settings, the positive
supply current reaches 140mA and the negative supply
current can be 35mA. Operating at +/-5V power supply, the
total power dissipation is:
PD = 5*140mA + 5*35mA = 875mW
θ
calculated. This is done using the equation:
θ
Where
Tj is the maximum junction temperature (135°C)
Ta is the maximum ambient temperature (85°C)
For a QFN 20 package in a properly layout PCB heatsinking
copper area, 40C/W θ
achieved. To disperse the heat, the bottom heatspeader
must be soldered to the PCB. Heat flows through the
heatspeader to the circuit board copper then spreads and
convects to air. Thus the PCB copper plane becomes the
headsink (see TB389). This has proven to be a very effective
technique. A separate application note details the 20 pin
QFN PCB design considerations is available.
JA
JA
required for long term reliable operation can be
= (Tj - Ta)/PD = 57C/W
16
12
+
+
+
CENABLE 7
14
JA
G_out
B_out
R_out
X2
thermal resistance can be
15
13
11
20
October 12, 2006
FN7441.3