at89lv55 ATMEL Corporation, at89lv55 Datasheet - Page 8

• Manufacturer Part Number: at89lv55
• Description: At89lv55 8-bit Microcontroller With 20k Bytes Flash
• Manufacturer: ATMEL Corporation

6. Data Memory
7. Timer 0 and 1
8. Timer 2
8
AT89LV55
The AT89LV55 implements 256 bytes of on-chip RAM. The upper 128 bytes occupy a parallel
address space to the Special Function Registers. That means the upper 128 bytes have the
same addresses as the SFR space but are physically separate from SFR space.
When an instruction accesses an internal location above address 7FH, the address mode used
in the instruction specifies whether the CPU accesses the upper 128 bytes of RAM or the SFR
space. Instructions that use direct addressing access SFR space.
For example, the following direct addressing instruction accesses the SFR at location 0A0H
(which is P2).
Instructions that use indirect addressing access the upper 128 bytes of RAM. For example, the
following indirect addressing instruction, where R0 contains 0A0H, accesses the data byte at
address 0A0H, rather than P2 (whose address is 0A0H).
Note that stack operations are examples of indirect addressing, so the upper 128 bytes of data
RAM are available as stack space.
Timer 0 and Timer 1 in the AT89LV55 operate the same way as Timer 0 and Timer 1 in the
AT89C51. For further information on the timers’ operation, please click on the document link
below:
Timer 2 is a 16-bit Timer/Counter that can operate as either a timer or an event counter. The
type of operation is selected by bit C/T2 in the SFR T2CON (shown in
three operating modes: capture, auto-reload (up or down counting), and baud rate generator.
The modes are selected by bits in T2CON, as shown in
Timer 2 consists of two 8-bit registers, TH2 and TL2. In the Timer function, the TL2 register is
incremented every machine cycle. Since a machine cycle consists of 12 oscillator periods, the
count rate is 1/12 of the oscillator frequency.
In the Counter function, the register is incremented in response to a 1-to-0 transition at its corre-
sponding external input pin, T2. In this function, the external input is sampled during S5P2 of
every machine cycle. When the samples show a high in one cycle and a low in the next cycle,
the count is incremented. The new count value appears in the register during S3P1 of the cycle
following the one in which the transition was detected. Since two machine cycles (24 oscillator
periods) are required to recognize a 1-to-0 transition, the maximum count rate is 1/24 of the
oscillator frequency. To ensure that a given level is sampled at least once before it changes, the
level should be held for at least one full machine cycle.
MOV 0A0H, #data
MOV @R0, #data
http://www.atmel.com/dyn/resources/prod_documents/DOC4316.PDF
Table
8-1.
Table
5-2). Timer 2 has
0811D–MICRO–3/06