at89lp2052-20xi ATMEL Corporation, at89lp2052-20xi Datasheet - Page 16

• Manufacturer Part Number: at89lp2052-20xi
• Description: At89lp2052 8-bit Microcontroller With 2/4-kbyte Flash
• Manufacturer: ATMEL Corporation

14.1
16
Interrupt Response Time
AT89LP2052/LP4052
The Timer 0 and Timer 1 Interrupts are generated by TF0 and TF1, which are set by a rollover in
their respective Timer/Counter registers (except for Timer 0 in Mode 3). When a timer interrupt is
generated, the on-chip hardware clears the flag that generated it when the service routine is
vectored to.
The Serial Port Interrupt is generated by the logic OR of RI and TI in SCON plus SPIF in SPSR.
None of these flags is cleared by hardware when the service routine is vectored to. In fact, the
service routine normally must determine whether RI, TI, or SPIF generated the interrupt, and the
bit must be cleared by software.
The CF bit in ACSR generates the Comparator Interrupt. The flag is not cleared by hardware
when the service routine is vectored to and must be cleared by software.
Most of the bits that generate interrupts can be set or cleared by software, with the same result
as though they had been set or cleared by hardware. That is, interrupts can be generated and
pending interrupts can be canceled in software. The exception is the SPI interrupt flag SPIF.
This flag is only set by hardware and may only be cleared by software.
Table 14-1.
The interrupt flags may be set by their hardware in any clock cycle. The interrupt controller polls
the flags in the last clock cycle of the instruction in progress. If one of the flags was set in the
preceding cycle, the polling cycle will find it and the interrupt system will generate an LCALL to
the appropriate service routine as the next instruction, provided that the interrupt is not blocked
by any of the following conditions: an interrupt of equal or higher priority level is already in
progress; the instruction in progress is RETI or any write to the IE, IP, or IPH registers. Either of
these conditions will block the generation of the LCALL to the interrupt service routine. The sec-
ond condition ensures that if the instruction in progress is RETI or any access to IE, IP or IPH,
then at least one more instruction will be executed before any interrupt is vectored to. The poll-
ing cycle is repeated at the last cycle of each instruction, and the values polled are the values
that were present at the previous clock cycle. If an active interrupt flag is not being serviced
because of one of the above conditions and is no longer active when the blocking condition is
removed, the denied interrupt will not be serviced. In other words, the fact that the interrupt flag
was once active but not serviced is not remembered. Every polling cycle is new.
Interrupt
System Reset
External Interrupt 0
Timer 0 Overflow
External Interrupt 1
Timer 1 Overflow
Serial Port
Reserved
Analog Comparator
Interrupt Vector Addresses
CF
Source
RST or POR or BOD
IE0
TF0
IE1
TF1
RI or TI or SPIF
–
Vector Address
3547H–MICRO–5/07
000BH
001BH
002BH
0000H
0003H
0013H
0023H
0033H