at89lp214-20xi ATMEL Corporation, at89lp214-20xi Datasheet - Page 19
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at89lp214-20xi
Manufacturer Part Number
at89lp214-20xi
Description
At89lp213 8-bit Microcontroller With 2k Bytes Flash
Manufacturer
ATMEL Corporation
Datasheet
1.AT89LP214-20XI.pdf
(89 pages)
3538B–MICRO–11/07
instruction, an internal polling sequence determines which request is serviced. The polling
sequence is based on the vector address; an interrupt with a lower vector address has higher
priority than an interrupt with a higher vector address. Note that the polling sequence is only
used to resolve pending requests of the same priority level.
The External Interrupts INT0 and INT1 can each be either level-activated or edge-activated,
depending on bits IT0 and IT1 in Register TCON. The flags that actually generate these inter-
rupts are the IE0 and IE1 bits in TCON. When the service routine is vectored to, hardware clears
the flag that generated an external interrupt only if the interrupt was edge-activated. If the inter-
rupt was level activated, then the external requesting source (rather than the on-chip hardware)
controls the request flag.
The Timer 0 and Timer 1 Interrupts are generated by TF0 and TF1, which are set by a rollover in
their respective Timer/Counter registers (except for Timer 0 in Mode 3). When a timer interrupt is
generated, the on-chip hardware clears the flag that generated it when the service routine is
vectored to.
The Serial Port Interrupt is generated by the logic OR of RI and TI in SCON plus SPIF in SPSR.
None of these flags is cleared by hardware when the service routine is vectored to. In fact, the
service routine normally must determine whether RI, TI, or SPIF generated the interrupt, and the
bit must be cleared by software.
A logic OR of all eight flags in the GPIF register causes the general-purpose interrupt. None of
these flags is cleared by hardware when the service routine is vectored to. The service routine
must determine which bit generated the interrupt, and the bit must be cleared in software. If the
interrupt was level activated, then the external requesting source must de-assert the interrupt
before the flag may be cleared by software.
The CF bit in ACSR generates the Comparator Interrupt. The flag is not cleared by hardware
when the service routine is vectored to and must be cleared by software.
Most of the bits that generate interrupts can be set or cleared by software, with the same result
as though they had been set or cleared by hardware. That is, interrupts can be generated and
pending interrupts can be canceled in software. The two exceptions are the SPI interrupt flag
SPIF and the general-purpose interrupt flags in GPIF. These flags are only set by hardware and
may only be cleared by software.
Table 12-1.
Interrupt
System Reset
External Interrupt 0
Timer 0 Overflow
External Interrupt 1
Timer 1 Overflow
Serial Port
General-purpose Interrupt
Analog Comparator
Interrupt Vector Addresses
Source
RST or POR or BOD
IE0
TF0
IE1
TF1
RI or TI or SPIF
GPIF
CF
AT89LP213/214
Vector Address
000BH
001BH
002BH
0000H
0003H
0013H
0023H
0033H
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