m66281fp Renesas Electronics Corporation., m66281fp Datasheet
m66281fp
Available stocks
Related parts for m66281fp
m66281fp Summary of contents
Page 1
... The M66281FP is high speed line memory that uses high performance silicon gate CMOS process technology and adopts the FIFO (First In First Out) structure consisting of 5120 words × 8 bits × 2. Since memory is available to simultaneously output 1 line delay and 2 line delay data, the M66281FP is optimal for the compensation of data of multiple lines. ...
Page 2
... M66281FP Pin Arrangement NC 39 RCK 40 RRESB 41 REB 42 GND Q00 45 Q01 46 Q02 REJ03F0254-0200 Rev.2.00 Sep 14, 2007 Page M66281FP (Top view) Outline: PRQP0048JA-A (48P6S- NC: No connection ...
Page 3
... M66281FP Absolute Maximum Ratings Item Supply voltage Input voltage Output voltage Power dissipation Storage temperature 63°C. Ta > 63°C are derated at − °C Note: * Recommended Operating Conditions Item Supply voltage Supply voltage Operating temperature Electrical Characteristics Item High-level input voltage ...
Page 4
... M66281FP Function When write enable input WEB is set to "L", the contents of data inputs are written into memory only for 1 line delay data in synchronization with a rising edge of write clock input WCK to perform writing operation. When this is the case, the write address counter of memory only for 1 line delay data is incremented simultaneously. ...
Page 5
... M66281FP Switching Characteristics Item Access time Output hold time Output enable time Output disable time Timing Requirements Item Write clock (WCK) cycle Write clock (WCK) "H" pulse width Write clock (WCK) "L" pulse width Read clock (RCK) cycle Read clock (RCK) "H" pulse width Read clock (RCK) " ...
Page 6
... M66281FP Switching Characteristics Measurement Circuit pF Input pulse level Input pulse up/down time Judging voltage Input: 1.3 V Output: 1.3 V (However, t judged with 90% of the output amplitude) Load capacitance C includes the floating capacity of connected lines and input capacitance of probe. ...
Page 7
... M66281FP Operation Timing Write Cycle n cycle cycle WCK t t WCK WCKH WEB Dn (n) Write Reset Cycle n − 1 cycle n cycle WCK t t WCK NRESH WRESB (n − REJ03F0254-0200 Rev.2.00 Sep 14, 2007 Page cycle Disable cycle WCKL WEH ...
Page 8
... M66281FP Matters that Needs Attention when WCK Stops n cycle cycle WCK t WCK WEB (n) Period for writing data (n) into memory Input data of n cycle is read at the rising edge after WCK of n cycle and writing operation starts in the WCK low-level period cycle ...
Page 9
... M66281FP Read Cycle n cycle cycle RCK t t RCK RCKH REB Q0n (n) (Q1n) Read Reset Cycle n − 1 cycle n cycle RCK t t RCK NRESH RRESB Q0n (n − 1) (Q1n) REJ03F0254-0200 Rev.2.00 Sep 14, 2007 Page cycle Disable cycle RCKL REH ...
Page 10
... M66281FP Notes on Reading of Written Data in Read Disable When writing operation is performed at n cycle and cycle on the writing side in the read disable period after n − 1 cycle on the reading side, output at n cycle and cycle after read enable is invalid. For output cycle and after, however, data written in the read disable period output. n − ...
Page 11
... M66281FP Variable Length Delay Bit 1 Line (5120 Bits) Delay Input data can be written at the rising edge of WCK after write cycle and output data is read at the rising edge of RCK before read cycle to easily make 1 line delay. 0 cycle 1 cycle WCK RCK t t RESS ...
Page 12
... M66281FP n-bit Delay 2 (Slides input timings of WRESB and RRESB at cycles according to the delay length) 0 cycle 1 cycle WCK RCK t t RESS RESH WRESB RRESB (0) Q0n (Q1n) n-bit Delay 3 (Slides address by disabling REB in the period according to the delay length) 0 cycle ...
Page 13
... M66281FP Reading Shortest n-cycle Write Data "n" (Reading side n − 2 cycle ends after the end of writing side cycle) When the reading side n − 2 cycle ends before the end of the writing side cycle, output cycle is made invalid. In the following diagram, end of reading side n − 2 cycle and end of writing side cycle overlap each other. ...
Page 14
... M66281FP Application Example Sub Scan Resolution Compensation Circuit with Laplacian Filter M66281 line image data 1 line delay Q10 to Q17 2 line delay Main scan direction REJ03F0254-0200 Rev.2.00 Sep 14, 2007 Page line image data Q00 to Q07 × − ...
Page 15
... M66281FP Package Dimensions JEITA Package Code RENESAS Code P-QFP48-7x10-0.65 PRQP0048JA Index mark REJ03F0254-0200 Rev.2.00 Sep 14, 2007 Page Previous Code MASS[Typ.] 48P6S-A 0. NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. ...
Page 16
Notes: 1. This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained ...