m66256fp Renesas Electronics Corporation., m66256fp Datasheet - Page 9

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m66256fp

Manufacturer Part Number
m66256fp
Description
5120 ? 8-bit Line Memory Fifo
Manufacturer
Renesas Electronics Corporation.
Datasheet

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M66256FP
Variable Length Delay Bits
1-line (5120 Bits) Delay
A write input data is written into memory at the second rise edge of WCK in the cycle, and a read output data is output
from memory at the first rise edge of RCK in the cycle, so that 1-line delay can be made easily.
N-bit Delay Bit
(Making a reset at a cycle corresponding to delay length)
REJ03F0250-0200 Rev.2.00 Sep 14, 2007
Page 9 of 13
WCK
RCK
WRES
RRES
Dn
Qn
WRES
RRES
WCK
RCK
Dn
Qn
t
t
RESS
RESS
t
t
RESH
RESH
Cycle 0
Cycle 0
t
t
DS
DS
(0)
(0)
t
t
DH
DH
Cycle 1
Cycle 1
(1)
(1)
Cycle 2
Cycle 2
5120 cycles
m cycles
(2)
(2)
(5117)
(n − 3)
Cycle 5118 Cycle 5119
Cycle n − 2 Cycle n − 1
(5118)
(n − 2)
t
RESS
(5119)
(n − 1)
t
Cycle 5120
RESH
t
Cycle n
t
AC
AC
(0')
(0')
t
t
DS
DS
(0')
(0)
(0')
(0)
t
t
t
t
Cycle 5121
Cycle n + 1
DH
OH
DH
OH
(1')
(1')
(1')
(1)
(1')
(1)
Cycle 5122
Cycle n + 2
(2')
(2')
(2')
(2)
(2')
(2)
WE, RE = "L"
m ≥ 3
WE, RE = "L"
Cycle n + 3
(3')
(3')
(3')
(3)
(3)

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