xccace-tq144 Xilinx Corp., xccace-tq144 Datasheet - Page 14

• Manufacturer Part Number: xccace-tq144
• Description: Ic Ace Controller Chip Tq144
• Manufacturer: Xilinx Corp.

System ACE CompactFlash Solution
Single Register Write Cycle
The single register write cycle is shown in
gle register write is accomplished by asserting a valid
address (MPA), asserting the chip enable (MPCE = LOW)
and de-asserting the output enable (MPOE = HIGH) during
the first clock cycle (Cycle 0). These signals should hold
these values at least until the rising edge of the third clock
cycle (Cycle 2).
14
CYCLE
CLK
MPA
MPD
MPCE
MPWE
MPOE
60ns
Figure 10: Single WORD Write to an ACE Register
Cycle 0
Figure
80ns
ADDRESS
10. A sin-
tSOE
tSCE
tSA
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100ns
Cycle 1
tSWE
tSD
The write enable signal should be asserted (MPWE = LOW)
during the second clock cycle (Cycle 1). Data (MPD) to be
written to the specified address should be asserted during
the same clock cycle that the write enable is asserted
(Cycle 1). The register write cycle is then completed by
de-asserting the write enable during the third clock cycle
(Cycle 2).
DATA
120ns
tH
tH
tH
tH
tH
Cycle 2
tSWE
140ns
DS080 (v2.0) October 1, 2008
DS080_15_013101
tH
Cycle 3
Product Specification
160 s
R