lan9313 Standard Microsystems Corp., lan9313 Datasheet - Page 44

• Manufacturer Part Number: lan9313
• Description: Lan9313/lan9313i Three Port 10/100 Managed Ethernet Switch With Mii
• Manufacturer: Standard Microsystems Corp.

Revision 1.2 (04-08-08)
4.2.3.1
4.2.3.2
4.2.3.3
Port 2 PHY Reset
A Port 2 PHY reset is performed by setting the PHY2_RST bit of the
(RESET_CTL)
Upon completion of the Port 2 PHY reset, the PHY2_RST and Reset bits are automatically cleared.
No other modules of the LAN9313/LAN9313i are affected by this reset.
In addition to the methods above, the Port 2 PHY is automatically reset after returning from a PHY
power-down mode. This reset differs in that the PHY power-down mode reset does not reload or reset
any of the PHY registers. Refer to
information.
Port 2 PHY reset completion can be determined by polling the PHY2_RST bit in the
Register (RESET _CTL)
(PHY_BASIC_CONTROL_x)
clear approximately 110uS after the Port 2 PHY reset occurrence.
Note: When using the Reset bit to reset the Port 2 PHY, register bits designated as NASR are not
Refer to
Port 1 PHY Reset
A Port 1 PHY reset is performed by setting the PHY1_RST bit of the
(RESET_CTL)
Upon completion of the Port 1 PHY reset, the PHY1_RST and Reset bits are automatically cleared.
No other modules of the LAN9313/LAN9313i are affected by this reset.
In addition to the methods above, the Port 1 PHY is automatically reset after returning from a PHY
power-down mode. This reset differs in that the PHY power-down mode reset does not reload or reset
any of the PHY registers. Refer to
information.
Port 1 PHY reset completion can be determined by polling the PHY1_RST bit in the
Register (RESET _CTL)
(PHY_BASIC_CONTROL_x)
clear approximately 110uS after the Port 1 PHY reset occurrence.
Note: When using the Reset bit to reset the Port 1 PHY, register bits designated as NASR are not
Refer to
Virtual PHY Reset
A Virtual PHY reset is performed by setting the VPHY_RST bit of the
(RESET_CTL)
modules of the LAN9313/LAN9313i are affected by this reset.
Virtual PHY reset completion can be determined by polling the VPHY_RST bit in the
Register (RESET_CTL)
(VPHY_BASIC_CTRL)
approximately 1uS after the Virtual PHY reset occurrence.
Refer to
resets.
reset.
reset.
Section 7.2.10, "PHY Resets," on page 97
Section 7.2.10, "PHY Resets," on page 97
Section 7.3.3, "Virtual PHY Resets," on page 100
or the Reset bit in the
or the Reset bit in the
or Reset in the
until it clears. Under normal conditions, the VPHY_RST and Reset bit will clear
or the Reset bit in the
or the Reset bit in the
until it clears. Under normal conditions, the PHY2_RST and Reset bit will
or the Reset bit in the
until it clears. Under normal conditions, the PHY1_RST and Reset bit will
Virtual PHY Basic Control Register
Section 7.2.9, "PHY Power-Down Modes," on page 96
Section 7.2.9, "PHY Power-Down Modes," on page 96
DATASHEET
Port x PHY Basic Control Register
Port x PHY Basic Control Register
44
for additional information on Port 2 PHY resets.
for additional information on Port 1 PHY resets.
Virtual PHY Basic Control Register
Port x PHY Basic Control Register
Port x PHY Basic Control Register
for additional information on Virtual PHY
Three Port 10/100 Managed Ethernet Switch with MII
(VPHY_BASIC_CTRL). No other
(PHY_BASIC_CONTROL_x).
(PHY_BASIC_CONTROL_x).
Reset Control Register
Reset Control Register
Reset Control Register
SMSC LAN9313/LAN9313i
Reset Control
Reset Control
Reset Control
for additional
for additional
Datasheet