lan9312 Standard Microsystems Corp., lan9312 Datasheet - Page 439
lan9312
Manufacturer Part Number
lan9312
Description
Lan9312 High Performance Two Port 10/100 Managed Ethernet Switch With 32-bit Non-pci Cpu Interface
Manufacturer
Standard Microsystems Corp.
Datasheet
1.LAN9312.pdf
(458 pages)
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High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface
Datasheet
SMSC LAN9312
14.5.4.27
31:14
13:10
BITS
9:8
7
RESERVED
Drop Reason B
When bit 7 is set, these bits indicate the reason a packet was dropped per
the table below:
Source Port B
When bit 7 is set, these bits indicate the source port on which the packet
was dropped.
00 = Port 0
01 = Port 1
10 = Port 2
11 = RESERVED
Status B Pending
When set, bits 13:8 are valid.
VALUES
Buffer Manager Interrupt Pending Register (BM_IPR)
This register contains the Buffer Manager interrupt status. The status is double buffered. All interrupts
in this register may be masked via the
Refer to
0000
0001
0010
0100
0101
1000
1001
1010
0011
0110
0111
1011
1100
1101
1110
1111
BIT
Register #:
Chapter 5, "System Interrupts," on page 49
The destination address was not in the ALR table (unknown or broadcast), and
the Broadcast Buffer Level was exceeded.
Drop on Red was set and the packet was colored Red.
There were no buffers available.
There were no memory descriptors available.
The destination address was not in the ALR table (unknown or broadcast) and
there were no valid destination ports.
The packet had a receive error and was >64 bytes
The Buffer Drop Level was exceeded.
RESERVED
RESERVED
Drop on Yellow was set, the packet was colored Yellow and was randomly
selected to be dropped.
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
1C21h
DESCRIPTION
DESCRIPTION
DATASHEET
Buffer Manager Interrupt Mask Register (BM_IMR)
439
Size:
for more information.
32 bits
TYPE
RO
RC
RC
RC
Revision 1.2 (04-08-08)
DEFAULT
00b
0h
0b
-
register.
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