mc33596 Freescale Semiconductor, Inc, mc33596 Datasheet - Page 24

• Manufacturer Part Number: mc33596
• Description: Pll Tuned Uhf Receiver For Data Transfer Applications
• Manufacturer: Freescale Semiconductor, Inc

Received Signal Strength Indicator (RSSI)
The information from the LNA AGC is available in digital form in the four most significant bits of status
register RSSI.
The whole content of status register RSSI provides 2 x 4 bits of RSSI information about the incoming
signal (see
Figure 15
The quasi peak detector (D1, R1, C1) has a charge time of about 20 μs to avoid sensitivity to spikes.
R2 controls the decay time constant of about 5 ms to allow efficient smoothing of the OOK modulated
signal at low data rates. This time constant is useful in continuous mode when S2 is permanently closed.
To allow high-speed RSSI updating in peak pulse measurement, a discharge circuit (S1) is required to reset
the measured voltage and to allow new peak detection.
S2 is used to sample the RSSI voltage to allow peak pulse measurement (S2 used as sample and hold), or
to allow continuous transparent measurement (S2 continuously closed).
The 4-bit analog-to-digital convertor (ADC) is based on a flash architecture. The conversion time is
16 x T
on a 32 x T
If RSSIE is reset, the whole RSSI module is switched off, reducing the current consumption. The output
buffer connected to RSSIOUT is set to high impedance.
15.2 Operation
Two modes of operation are available: sample mode and continuous mode.
15.2.1 Sample Mode
Sample mode allows the peak power of a specific pulse in an incoming frame to be measured.
The quasi peak detector is reset by closing S1. After 7 x T
is set high. On the falling edge of RSSIC, S2 is opened. The voltage on RSSIOUT is sampled and held.
The last RSSI conversion results are stored in the RSSI register and no further conversion is done.
24
IF Filter Output
diglck
shows a simplified block diagram of the RSSI function.
Section 16.6, “RSSI
digclk
. As a single convertor is used for the two analog signals, the RSSI register content is updated
timebase.
Register”).
Figure 15. RSSI Simplified Block Diagram
Σ
MC33596 Data Sheet, Rev. 3
LNA AGC Out
D1
R1
digclk
C1
, S1 is released. S2 is closed when RSSIC
R2
S1
ADC
Freescale Semiconductor
MSB
S2
C2
RSSI Register
RSSIOUT
LSB